airisc_core_complex
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors. (by Fraunhofer-IMS)
friscv
RISCV CPU implementation in SystemVerilog (by dpretet)
airisc_core_complex | friscv | |
---|---|---|
1 | 1 | |
71 | 15 | |
- | - | |
4.8 | 7.7 | |
6 months ago | 8 days ago | |
Verilog | Coq | |
GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
airisc_core_complex
Posts with mentions or reviews of airisc_core_complex.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-10.
friscv
Posts with mentions or reviews of friscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-22.
What are some alternatives?
When comparing airisc_core_complex and friscv you can also consider the following projects:
riscv - RISC-V CPU Core (RV32IM)
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Hazard3 - 3-stage RV32IMACZb* processor with debug
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
biriscv - 32-bit Superscalar RISC-V CPU
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog