airisc_core_complex VS Hazard3

Compare airisc_core_complex vs Hazard3 and see what are their differences.

airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors. (by Fraunhofer-IMS)

Hazard3

3-stage RV32IMACZb* processor with debug (by Wren6991)
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airisc_core_complex Hazard3
1 1
70 70
- -
4.8 7.2
6 months ago 6 days ago
Verilog Verilog
GNU General Public License v3.0 or later Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

airisc_core_complex

Posts with mentions or reviews of airisc_core_complex. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-11-10.

Hazard3

Posts with mentions or reviews of Hazard3. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-09-06.

What are some alternatives?

When comparing airisc_core_complex and Hazard3 you can also consider the following projects:

riscv - RISC-V CPU Core (RV32IM)

oblivious-cpu - A re-implementation of ShapeCPU

friscv - RISCV CPU implementation in SystemVerilog

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

biriscv - 32-bit Superscalar RISC-V CPU

fpga_riscv_cpu - fpga verilog risc-v rv32i cpu

serv - SERV - The SErial RISC-V CPU

riscv-isa-manual - RISC-V Instruction Set Manual