airisc_core_complex VS friscv

Compare airisc_core_complex vs friscv and see what are their differences.

airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors. (by Fraunhofer-IMS)
risc-v Riscv Fpga Verilog Embedded Systems AI Asic smart-sensors asil functional-safety Safety Security
Source Code
airisc.de
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friscv

RISCV CPU implementation in SystemVerilog (by dpretet)
riscv-cpu Riscv Rv32i Verilog Systemverilog Fpga Asic risc-v Assembler fpga-soc asic-design Axi4 axi4-protocol crossbar
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airisc_core_complex friscv
1 1
70 15
- -
4.8 7.7
6 months ago 7 days ago
Verilog Coq
GNU General Public License v3.0 or later MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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airisc_core_complex

Posts with mentions or reviews of airisc_core_complex. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-11-10.

friscv

Posts with mentions or reviews of friscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-22.

What are some alternatives?

When comparing airisc_core_complex and friscv you can also consider the following projects:

riscv - RISC-V CPU Core (RV32IM)

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Hazard3 - 3-stage RV32IMACZb* processor with debug

ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

biriscv - 32-bit Superscalar RISC-V CPU

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

airisc_core_complex vs riscv friscv vs darkriscv airisc_core_complex vs Hazard3 friscv vs ravenoc airisc_core_complex vs biriscv friscv vs scr1