RapidStream
edalize
| RapidStream | edalize | |
|---|---|---|
| 2 | 4 | |
| 9 | 592 | |
| - | - | |
| 0.0 | 7.2 | |
| almost 2 years ago | 9 days ago | |
| Python | Python | |
| MIT License | BSD 2-clause "Simplified" License |
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RapidStream
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Drumroll! 5-7x faster compilation for Xilinx.
RapidStream
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Ultra-Fast Parallel Placement and Routing for Vivado HLS Dataflow Designs!
Please take a look at our repo, RapidStream, and please we appreciate it if you can give a star⭐️ to our repo if you like the idea! https://github.com/Licheng-Guo/RapidStream
edalize
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Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
[1]: https://github.com/olofk/edalize
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
What are some alternatives?
fusesoc_template - Example of how to get started with olofk/fusesoc.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
entangle - A lightweight (serverless) native python parallel processing framework based on simple decorators and call graphs.
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
apio - :seedling: Open source ecosystem for open FPGA boards
icestudio - :snowflake: Visual editor for open FPGA boards
rggen - Code generation tool for control and status registers
sphinx-vhdl
opentitan - OpenTitan: Open source silicon root of trust
hdl_checker - Repurposing existing HDL tools to help writing better code
serv - SERV - The SErial RISC-V CPU