OpenSERDES
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology. (by SparcLab)
litex
Build your hardware, easily! (by enjoy-digital)
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| OpenSERDES | litex | |
|---|---|---|
| 1 | 29 | |
| 115 | 2,683 | |
| - | - | |
| 10.0 | 9.7 | |
| about 2 years ago | 2 days ago | |
| Verilog | C | |
| GNU General Public License v3.0 only | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
OpenSERDES
Posts with mentions or reviews of OpenSERDES.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-01-14.
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
But here is an open source ASIC-proven serdes block, [OpenSERDES](https://github.com/SparcLab/OpenSERDES). [Here's the paper describing it](https://arxiv.org/abs/2105.13256). It's only 2 Gb/s per link, but it seems like that would be enough to do DDR3. It is available on Skywater OpenPDK 130nm.
litex
Posts with mentions or reviews of litex.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-11-06.
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FPGA Dev Boards for $150 or Less
https://github.com/enjoy-digital/litex
they have tutorials, you can get compatible boards for around $20
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Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
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Sunset TCL scripts ?
LiteX is a great example of a Python-first flow. However, they have chosen not to subordinate the scripting environment to a GUI toolchain - EDA vendors are unlikely to choose the same trade.
- synthesizing and using the Ibex RISC-V core
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Been messing around with litex and migen on my Tang Primer 20K
To lean these: https://github.com/enjoy-digital/litex, https://github.com/m-labs/migen
- CPU design for college project
- How can I learn about RISC-V and use case? I want to do a project for begginers
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.
- LiteX: Build Hardware Easily
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Using FPGAs for computations as a beginner
I am interested in trying out FPGAs for the purpose of running specific calculations more efficiently. Since the calculations themselves are quite complex, I would need to be able to program in a relatively high-level language. I've seen that designing SoC in Python is possible, for example with Litex (https://github.com/enjoy-digital/litex) or Amaranth (https://github.com/amaranth-lang/). I don't want to spend hundreds of hours learning about FPGAs, but I'm prepared to take on a challenge.
What are some alternatives?
When comparing OpenSERDES and litex you can also consider the following projects:
OpenLANE-Sky130-Physical-Design-Workshop - Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
nmigen-tutorial - A tutorial for using nmigen
sirdez - Glorious Binary Serialization and Deserialization for TypeScript.
SpinalHDL - Scala based HDL
BlueCap - iOS Bluetooth LE framework
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
litedram - Small footprint and configurable DRAM core
SaxonSoc - SoC based on VexRiscv and ICE40 UP5K
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
verilog-ethernet - Verilog Ethernet components for FPGA implementation