OpenSERDES

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology. (by SparcLab)

OpenSERDES Alternatives

Similar projects and alternatives to OpenSERDES based on common topics and language

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better OpenSERDES alternative or higher similarity.

OpenSERDES reviews and mentions

Posts with mentions or reviews of OpenSERDES. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-01-14.
  • How Much Would It Cost For A Truly Open Source RISC-V SOC?
    5 projects | /r/RISCV | 14 Jan 2023
    But here is an open source ASIC-proven serdes block, [OpenSERDES](https://github.com/SparcLab/OpenSERDES). [Here's the paper describing it](https://arxiv.org/abs/2105.13256). It's only 2 Gb/s per link, but it seems like that would be enough to do DDR3. It is available on Skywater OpenPDK 130nm.

Stats

Basic OpenSERDES repo stats
1
115
10.0
about 2 years ago

SparcLab/OpenSERDES is an open source project licensed under GNU General Public License v3.0 only which is an OSI approved license.

The primary programming language of OpenSERDES is Verilog.

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