FPGA-SDcard-Reader
sdspi
| FPGA-SDcard-Reader | sdspi | |
|---|---|---|
| 1 | 4 | |
| 221 | 142 | |
| - | - | |
| 3.8 | 7.4 | |
| 8 months ago | 26 days ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 only | - |
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FPGA-SDcard-Reader
sdspi
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C++ Verification Testbench Best-Practice Resources?
I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
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Envisioning the Ultimate I2C Controller
You mean ... sort of like I did in this project? I implemented an SPI based controller, where the controller took care of all the bit-banging for you, but the CPU still needed to issue the commands as appropriate for the protocol?
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SoC FPGA design to ASIC
How about an SD card controller? I know I have a SPI based SD card controller, but the SDIO isn't that much harder. If you look hard enough you can find open source SDIO controllers.
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CPU DESIGN
There are also open source versions of many of the pieces you will need. I now use an open source crossbar interconnect for most of my designs. I use AutoFPGA to connect all the pieces together. I mentioned my flash controller above, but I also have a SD Card controller I've used quite successfully. I've also posted a UART to Wishbone bridge and discussed network debugging, both of which I use routinely with the ZipCPU. If for no other reason, these components allow me to load or update software on my CPU even after it's been placed into an FPGA. Of course, many of those components are tied to a Wishbone bus infrastructure. You may find you need a bridge of some type to connect different buses structures together--memory naturally tends to operate at one width and clock, video at another, and your CPU at another, so it helps at times to have a universal bus adapter kit handy.
What are some alternatives?
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
biriscv - 32-bit Superscalar RISC-V CPU
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
rggen - Code generation tool for control and status registers
wb2axip - Bus bridges and other odds and ends
OpenROAD - OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
dpll - A collection of phase locked loop (PLL) related projects
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
nybbleForth - Stack machine with 4-bit instructions
Rudi-RV32I - A rudimental RISCV CPU supporting RV32I instructions, in VHDL
videozip - A ZipCPU SoC for the Nexys Video board supporting video functionality