cascade VS hdlConvertor

Compare cascade vs hdlConvertor and see what are their differences.

cascade

A Just-In-Time Compiler for Verilog from VMware Research (by vmware-archive)
Fpga JIT just-in-time Verilog Hardware REPL

DISCONTINUED

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hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4 (by Nic30)
Parser Verilog Fpga Vhdl Systemverilog systemverilog-parser vhdl-parser verilog-parser antrl4 Python
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cascade hdlConvertor
1 1
422 264
- -
0.6 5.8
almost 3 years ago 3 months ago
C++ C++
GNU General Public License v3.0 or later MIT License
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cascade

Posts with mentions or reviews of cascade. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-05-23.
  • Who would benefit if there were an FPGA-only linux OS.
    3 projects | /r/FPGA | 23 May 2022
    I think VMWare did a just-in-time compilation for verilog called Cascade that I don't think ever got a lot of traction that seems to do parts of what you are looking for in that code first gets executed in a simulator until hardware-compilation is done in which case it is automatically migrated to the hardware/accelerated version. Sadly, the tool/project seems to have been shelved by VMWare and development has moved out into original author's private repo which I think itself may say something about the idea.

hdlConvertor

Posts with mentions or reviews of hdlConvertor. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-01-24.
  • VHDL backend
    2 projects | /r/FPGA | 24 Jan 2021
    Have you seen https://github.com/dalance/sv-parser, https://github.com/google/verible, https://github.com/alainmarcel/Surelog, https://github.com/Nic30/hdlConvertor? I think there was at least one more that I stumbled across, but can't find at the moment.

What are some alternatives?

When comparing cascade and hdlConvertor you can also consider the following projects:

AutoSA - AutoSA: Polyhedral-Based Systolic Array Compiler

circt - Circuit IR Compilers and Tools

DomesdayDuplicator - High-speed LaserDisc RF sampler

vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

naja-verilog - A standalone structural (gate-level) verilog parser

rggen - Code generation tool for control and status registers

Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler

edalize - An abstraction library for interfacing EDA tools

cascade vs AutoSA hdlConvertor vs circt cascade vs DomesdayDuplicator hdlConvertor vs vscode-terosHDL hdlConvertor vs naja-verilog hdlConvertor vs rggen hdlConvertor vs Surelog hdlConvertor vs verible hdlConvertor vs clash-ghc hdlConvertor vs edalize