verilator
Verilator open-source SystemVerilog simulator and lint system (by verilator)
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python (by cocotb)
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| verilator | cocotb | |
|---|---|---|
| 11 | 28 | |
| 2,083 | 1,599 | |
| 4.4% | 4.1% | |
| 9.8 | 9.7 | |
| 7 days ago | 5 days ago | |
| C++ | Python | |
| GNU Lesser General Public License v3.0 only | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
verilator
Posts with mentions or reviews of verilator.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-10-11.
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What's new for RISC-V in LLVM 17
You may want to check out Verilator:
https://verilator.org/
- How to run & simulate system verilog files on VScode?
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Choosing a Verification Methodology
relevant issue
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Designing Billions of Circuits with Code
One notable exception is Verilator which is growing fast and competes welll with commercial Verilog simulators (https://github.com/verilator/verilator)
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Error when running cocotb using cocotb-test
It is 4.106, check https://github.com/verilator/verilator/issues/2778 for more details.
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Verilator: Suggestions for verification framework?
Yeah, there is currently a bug and only one specific version of verilator works with cocotb (4.106). Hopefully it will be fixed soon. Go make noise here: https://github.com/verilator/verilator/issues/2778.
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Vitis HLS and Verilator
Okay, made it. Problem is, that my account is flagged as soon as I created it, I am marked as "spammy", and my "comments will only be shown in staff mode". https://github.com/verilator/verilator/issues/3159
- Attention to everyone that is using Verilator and C++! DO NOT update your GCC Package to version 11.1, because it will cause Verilator's object files to fail to compile properly. I have been dealing with this issue for four days straight and have only now found the solution. You have been warned.
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Systemverilog / verilog functional editor not like vivado
If you will help me with systemverilog black box discusion (I have very low systemverilog experience) and verilator will get update then I will upload on github plugin to Sublime Text which lint whole file every time when you stop typing. Currently I have plugin based on Vivado's compiler, but compilation of simple verilog file takes 1'400ms...
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eProcessor is a project that will create a open source RISC-V core for High Performance Computing (HPC)
You have verilator which is a open source simulator , so it is feasible that a "user" could fix a bug or implement a feature (i does not have to be some individual, a business or a university could do it to).
cocotb
Posts with mentions or reviews of cocotb.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-07-04.
-
Designing a Low Latency 10G Ethernet Core
The use of cocotb and pyuvm for verification
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How is Python used in test automation in embedded systems?
For FPGA/HDL work, there's cocotb
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Introducing CoHDL
At the moment, it is not possible to directly simulate synthesizable contexts. In principle, I could add a simulator to CoHDL. As a Python implementation, it would be orders of magnitude slower than other solutions. Instead, I am using Cocotb to validate the generated VHDL and for the unit tests in the GitHub repository. There is also some very, very experimental support for formal verification, but it will take some time for that to become usable.
- Use cocotb to test and verify chip designs in Python
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Trying to learn and work with FPGAs
On the topic of simulation, you don't have to restrict yourself to using Verilog or VHDL to write your test benches. For example, Verilator lets you write them in C++, cocotb lets you use Python, and if you use SpinalHDL you will drive the underlying simulator using Scala.
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Help understanding how this makefile works?
I know it might be difficult without much context, but this makefile is called by a top level makefile. very confused if lines 35-74 do anything. They seem to be a mix of real makefile syntax and just straight up comments. what do these lines do?
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COBS protocol decoder progress
Learn more about this here: https://www.cocotb.org/
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AXI-Stream meme
Also consider cocotb, this thread has some compelling arguments. I'd say as a student, learning industry tools isn't necessarily the best thing you could spend your time on. Getting fast at design AND verification, where you can maintain flow state and run better microexperiments means you will understand more, faster.
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cocotb
Have you tried looking at the mixed language example?
- We're trying to sort this out with some of our engineers, so please humor - Do you prefer VHDL or Verilog?
What are some alternatives?
When comparing verilator and cocotb you can also consider the following projects:
wavedrom - :ocean: Digital timing diagram rendering engine
cocotbext-axi - AXI interface modules for Cocotb
HLS-Tiny-Tutorials - This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL
cocotb-test - Unit testing for cocotb
riscv_vhdl - Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
amaranth - A modern hardware definition language and toolchain based on Python
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
chiselverify - A dynamic verification library for Chisel.
signalflip-js - verilator testbench w/ Javascript using N-API
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
SpinalHDL - Scala based HDL