upduino-projects
neo430
| upduino-projects | neo430 | |
|---|---|---|
| 3 | 3 | |
| 6 | 178 | |
| - | - | |
| 0.0 | 2.8 | |
| over 1 year ago | over 2 years ago | |
| VHDL | VHDL | |
| GNU General Public License v3.0 only | BSD 3-clause "New" or "Revised" License |
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upduino-projects
- Does any one knows the vhdl code for (7,4) hamming code decoder?
- Using HOSC_CORE (Lattice Radiant, Ice40up5k, Synplify Pro, VHDL)
-
https://np.reddit.com/r/FPGA/comments/mro9hr/using_hosc_core_lattice_radiant_ice40up5k/gvsk3vg/
That'll give you the 48MHz clk. In the open source toolchain, you'd just change HSOSC to SB_HFOSC. More information about how to use the open source toolchain for VHDL (ghdl + yosys + icestorm + nextpnr) can be found in a few repos: - https://github.com/nobodywasishere/upduino-projects - https://github.com/controversial/es4 - https://github.com/YosysHQ/fpga-toolchain
neo430
-
looking for 16 bit RISC ISA to implement on cyclon IV FPGA
If you insist on 16-bit you could check out the neo430
-
Newbie needs help on retro-computer creation.
If you want a good example of a CISC style CPU converted to an FPGA look at the Neo430 it is based on the TI MSP430.
- The NEO430 Processor
What are some alternatives?
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
serv - SERV - The SErial RISC-V CPU
es4 - Code for Tufts ES4 Intro to Digital Electronics
fpga_torture - 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
riscv-debug-dtm - 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
fpga-toolchain - Multi-platform nightly builds of open source FPGA tools
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
SoC - Github Repo for Embedded FPGA course by Vincent Claes