shecc
spu32
| shecc | spu32 | |
|---|---|---|
| 6 | 1 | |
| 1,045 | 60 | |
| 1.6% | - | |
| 8.7 | 0.0 | |
| 4 days ago | almost 2 years ago | |
| C | C | |
| BSD 2-clause "Simplified" License | MIT License |
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shecc
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A self-hosting and educational C optimizing compiler
Yes, consider the case of shecc. It requires just a handful of C code lines to interpret directives set in the C preprocessor. Unlike relying on existing tools like cpp, as, or ld, shecc stands alone as a minimalist cross-compiler. This design could be particularly beneficial for students delving into the study of compiler construction. See https://github.com/sysprog21/shecc/blob/master/src/lexer.c#L...
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Compiler Class
I'm looking at this one for a CPU design I've been working on. :)
https://github.com/jserv/shecc
- Shecc: Self-hosting and educational C compiler
- shecc: self-hosting and educational C compiler
- shecc: Self-hosting and educational C compiler
spu32
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Designing instruction decoder
You asked for "elegant and simple". Disregarding your request, here's how I decode RISC-V: https://github.com/maikmerten/spu32/blob/master/cpu/decoder.v
What are some alternatives?
dji-firmware-tools - Tools for handling firmwares of DJI products, with focus on quadcopters.
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
quasiSoC - No-MMU Linux capable RISC-V SoC designed to be useful.
coollang-2020-fs - Compiler of a small Scala subset
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
bsod-kernel-fuzzing - BSOD: Binary-only Scalable fuzzing Of device Drivers
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
amacc - Small C Compiler generating ELF executable Arm architecture, supporting JIT execution
cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
llvm-project - The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!