sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces (by ZipCPU)
wbicapetwo
Wishbone to ICAPE interface conversion (by ZipCPU)
| sdspi | wbicapetwo | |
|---|---|---|
| 4 | 2 | |
| 137 | 8 | |
| - | - | |
| 7.4 | 0.0 | |
| 8 days ago | about 4 years ago | |
| Verilog | Verilog | |
| - | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
sdspi
Posts with mentions or reviews of sdspi.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-11.
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C++ Verification Testbench Best-Practice Resources?
I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
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Envisioning the Ultimate I2C Controller
You mean ... sort of like I did in this project? I implemented an SPI based controller, where the controller took care of all the bit-banging for you, but the CPU still needed to issue the commands as appropriate for the protocol?
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SoC FPGA design to ASIC
How about an SD card controller? I know I have a SPI based SD card controller, but the SDIO isn't that much harder. If you look hard enough you can find open source SDIO controllers.
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CPU DESIGN
There are also open source versions of many of the pieces you will need. I now use an open source crossbar interconnect for most of my designs. I use AutoFPGA to connect all the pieces together. I mentioned my flash controller above, but I also have a SD Card controller I've used quite successfully. I've also posted a UART to Wishbone bridge and discussed network debugging, both of which I use routinely with the ZipCPU. If for no other reason, these components allow me to load or update software on my CPU even after it's been placed into an FPGA. Of course, many of those components are tied to a Wishbone bus infrastructure. You may find you need a bridge of some type to connect different buses structures together--memory naturally tends to operate at one width and clock, video at another, and your CPU at another, so it helps at times to have a universal bus adapter kit handy.
wbicapetwo
Posts with mentions or reviews of wbicapetwo.
We have used some of these posts to build our list of alternatives
and similar projects.
- Can an FPGA program itself?
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Xilinx ICAP issues
Perhaps an example design using the ICAPE2 port might help?
What are some alternatives?
When comparing sdspi and wbicapetwo you can also consider the following projects:
biriscv - 32-bit Superscalar RISC-V CPU
openarty - An Open Source configuration of the Arty platform
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
wb2axip - Bus bridges and other odds and ends
wbuart32 - A simple, basic, formally verified UART controller
dpll - A collection of phase locked loop (PLL) related projects
wbscope - A wishbone controlled scope for FPGA's
nybbleForth - Stack machine with 4-bit instructions
zipcpu - A small, light weight, RISC CPU soft core
Rudi-RV32I - A rudimental RISCV CPU supporting RV32I instructions, in VHDL