wbicapetwo
Wishbone to ICAPE interface conversion (by ZipCPU)
openarty
An Open Source configuration of the Arty platform (by ZipCPU)
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| wbicapetwo | openarty | |
|---|---|---|
| 2 | 6 | |
| 8 | 116 | |
| - | - | |
| 0.0 | 0.0 | |
| about 4 years ago | 3 months ago | |
| Verilog | Verilog | |
| - | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
wbicapetwo
Posts with mentions or reviews of wbicapetwo.
We have used some of these posts to build our list of alternatives
and similar projects.
- Can an FPGA program itself?
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Xilinx ICAP issues
Perhaps an example design using the ICAPE2 port might help?
openarty
Posts with mentions or reviews of openarty.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-11.
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C++ Verification Testbench Best-Practice Resources?
I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
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PPS detection/regeneration
The repo is the example design. It was used by software, though, that's not (currently) posted. A lot of math went into the coefficients as well--that's all in the software.
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AXI Quad SPI 3.2 Flash programming scripts
Here's the flash controller repo I use. There's a flash controller in there for SPI, Dual SPI, and Quad SPI. The Dual and Quad SPI controllers need a device specific startup script to get them into the right mode. This script should be fairly well explained by the comments. You should find at least one of these controllers that works for you. More recent versions of the controller have a Wishbone arbiter within them -- they're just not checked in the repo yet. (DSPI, QSPI). This makes it so the design fully supports two two Wishbone ports: a config port by which you can send any value and the memory mapped read port. (You can't use both at the same time.)
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Arty S7 - 2 different flash brands
You can compare my configuration file for the Spansion flash with my config file for the Micron flash to see that these are the only two hardware differences between the two
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FPGA and Simulation tools for Risc-V design
I'd then recommend Verilator for simulation testing--but only after your formal design checking is complete. You can find online C++ models of a QSPI flash, RAM, and a serial port which should be good enough to get you going here. When you are ready for more permanent storage, there's also a decent C++ model of an SD card (SPI only).
What are some alternatives?
When comparing wbicapetwo and openarty you can also consider the following projects:
biriscv - 32-bit Superscalar RISC-V CPU
zipcpu - A small, light weight, RISC CPU soft core