rocket-chip
microwatt
rocket-chip | microwatt | |
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12 | 19 | |
3,011 | 643 | |
1.0% | - | |
7.8 | 6.7 | |
6 days ago | 21 days ago | |
Scala | Verilog | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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rocket-chip
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Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
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RISC-V Pushes into the Mainstream
You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up.
[1] https://github.com/chipsalliance/rocket-chip
- Can anyone explain simply how OpenSource the RISC-V actually is?
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Stages of prototyping a RISC-V processor on an FPGA?
My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.
- FPGA for RISC-V Processor
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How are modern processors and their architecture designed?
More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
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Project ideas for RISC-V?
This would allow you to experiment with your own chip or something like [the RocketChip generator](https://github.com/chipsalliance/rocket-chip).
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Question: Does the 32bit version of Rocket still supports FPU
https://github.com/chipsalliance/rocket-chip/blob/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/system/Configs.scala#L28
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The First Affordable RISC-V Computer Designed to Run Linux
I don't know about the u74 specifically, but sifive does seem to invest in a open source risc-v core called rocket-chip.
microwatt
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Microwatt: A tiny Open POWER ISA softcore written in VHDL 2008
My favorite part of this project is the pretty large battery of test cases. A lot of chip rtl releases don't bother with open sourcing the verification too, and that's arguably more useful than the rtl in the first place.
https://github.com/antonblanchard/microwatt/tree/master/test...
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Arm wants to charge dramatically more for chip licenses
MicroWatt is the only one I know of.
https://github.com/antonblanchard/microwatt
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RISC-V Pushes into the Mainstream
I have several OpenPOWER systems, including the POWER9 I use as my usual desktop. Besides IBM and other server manufacturers like Tyan and Wistron, you can get them as Raptor workstations and servers.
If you want an OpenPOWER design to play with, look at Microwatt ( https://github.com/antonblanchard/microwatt ) which is complete enough to boot Linux.
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How long until RISC gets adopted for the desktop?
Not true, as of 2019 the power ISA is able to be used without needing to pay any royalties to ibm under the openpower foundation. There's already a few projects that have taken advantage of it such as libreSOC and Microwatt. Source code for various firmware components are also freely available pertaining to the power platform.
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Build Open Silicon with Google
https://github.com/antonblanchard/microwatt is an example of a Linux-capable 64-bit core that has been submitted on multiple Open MPW shuttles:
- Any raw binary generic platform-agnostic test roms for PowerPC?
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What would you think if the Amiga line jumped from PowerPc to RISC-V CPUs?
GitHub https://github.com/openpower-cores https://github.com/antonblanchard/microwatt
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Keeping POWER relevant in the open source world
At the other end of the scale, if anyone wants to play you can run a little openpower CPU on a FPGA with completely open source. https://github.com/antonblanchard/microwatt
It's capable of running Linux, some example docs are https://shenki.github.io/boot-linux-on-microwatt/
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What is your take on ISA architectures for FPGAs (x86, arm, risc-v)?
Why dismiss POWER or SPARC ? :-)
What are some alternatives?
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
chiselwatt - A tiny POWER Open ISA soft processor written in Chisel
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
midimonster - Multi-protocol control & translation software (ArtNet, MIDI, OSC, sACN, ...)
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Apollo-11 - Original Apollo 11 Guidance Computer (AGC) source code for the command and lunar modules.
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
OpenSkyStacker - Multi-platform stacker for deep-sky astrophotography.
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
VexRiscvBPluginGenerator
Cores-VeeR-EH1 - VeeR EH1 core
librealsense - IntelĀ® RealSenseā¢ SDK