rocket-chip VS cva6

Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up.

[1] https://github.com/chipsalliance/rocket-chip

My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.

More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip

We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip

This would allow you to experiment with your own chip or something like [the RocketChip generator](https://github.com/chipsalliance/rocket-chip).

https://github.com/chipsalliance/rocket-chip/blob/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/system/Configs.scala#L28

I don't know about the u74 specifically, but sifive does seem to invest in a open source risc-v core called rocket-chip.

Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)

The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.

I made a post about this here not too long ago, but I think it would be really useful to come up with a Vivado benchmark, in the form of a standardized large and representative design. I was curious about Alder Lake performance too, and compared my new 12700K workstation against my laptop with this open source RISC-V CPU: https://github.com/openhwgroup/cva6

When the OpenHW Group was created in 2019, I had some hope that Alibaba or NXP (who are in the OpenHW Group) would release an open hardware RISC-V processor, but it looks like they are not making any public commits to the CVA6 core, so I doubt that we are ever going to see the source code of Alibaba's XT910 or NXP's Chassis RISC-V processor.

Ariane is now cva6 (it moved to a industry supported non-profit).

At this stage, it could make sense for e.g. universities to start developing peripherals & controllers targeted at ASIC rather than creating yet-another-core (https://riscv.org/exchange/cores-socs/ has 107 lines already for cores), leveraging an OSHW ASIC-proven core from e.g. the OpenHW group (https://github.com/openhwgroup/cva6). Manufacturing in not-so-old processes is affordable for teaching institutions (e.g. https://europractice-ic.com/ in Europe), and taping out working cores is no longer a 'new' thing (e.g. http://asic.ethz.ch/all/years.html ).

Looking at the github of the openhw group looks like the license is granting patents to the project. So it looks ok.