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Most of them might still be missing on the ASIC side, but already exist to some extent on the FPGA side. Litex (https://github.com/enjoy-digital/litex/) is adding support for the USB host (ohci-compatible) developed for Saxon (https://github.com/SpinalHDL/SaxonSoc), in addition to the DRAM, Ethernet (MII, GMII, some RGMII), micro-sd, UART, HDMI framebuffer, ... peripherals that are already supported.
Most of them might still be missing on the ASIC side, but already exist to some extent on the FPGA side. Litex (https://github.com/enjoy-digital/litex/) is adding support for the USB host (ohci-compatible) developed for Saxon (https://github.com/SpinalHDL/SaxonSoc), in addition to the DRAM, Ethernet (MII, GMII, some RGMII), micro-sd, UART, HDMI framebuffer, ... peripherals that are already supported.
At this stage, it could make sense for e.g. universities to start developing peripherals & controllers targeted at ASIC rather than creating yet-another-core (https://riscv.org/exchange/cores-socs/ has 107 lines already for cores), leveraging an OSHW ASIC-proven core from e.g. the OpenHW group (https://github.com/openhwgroup/cva6). Manufacturing in not-so-old processes is affordable for teaching institutions (e.g. https://europractice-ic.com/ in Europe), and taping out working cores is no longer a 'new' thing (e.g. http://asic.ethz.ch/all/years.html ).
So for instance (and AFAI understand...) the DDR2 sdram controller uses a generic PHY (https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/gensdrphy.py) , but the DDR3 one has to talk to some vendor-specific PHY (e.g. https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s7ddrphy.py ). The controller itself is vendor-agnostic (https://github.com/enjoy-digital/litedram/blob/master/litedram/core/controller.py). On Xilinx FPGA it doesn't rely on MIG at all.