What do think of Chisel HDL? is it worth learning over Verilog/SystemVerilog?

• VexRiscv

  21 2,252 7.6 Assembly

  A FPGA friendly 32 bit RISC-V CPU implementation

  

I really like Chisel HDL or any other new HDL languages like SpinalHDL or migen b/c it allows you to create some very complex yet modular designs. See VexRiscv or LiteX for instance. Languages like this exist b/c there is a need for it, but I wouldn't say that you should learn these new languages over verilog. All these languages output verilog/VHDL for now, but there is work being to done eliminate the need for outputting verilog; eventually, Chisel will output an open source CIRCT IR. Hope is to get EDA vendors to support this IR which I'm sure will take a while. For now, you should definitely learn Verilog or VHDL before Chisel.

• Rosebud

  2 31 0.0 Verilog

  Framework for FPGA-accelerated Middlebox Development

  

Sure, I suppose trivial code might be somewhat readable. But doing something non-trivial is a different story. For example, this is what spinal HDL generates for vexriscv: https://github.com/ucsdsysnet/Shire/blob/master/fpga_src/lib/Shire/rtl/VexRiscv.v. This isn't exactly readable. There are about 320 _zz_ signals in there that presumably didn't exist in the original scala code.

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• tensil

  12 319 0.0 Scala

  Open source machine learning accelerators

  

www.tensil.ai

• chisel-book

  4 697 8.1 TeX

  Digital Design with Chisel

Sure. You can follow this little .pdf: https://github.com/schoeberl/chisel-book

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