riscv-debug-dtm
neorv32-setups
| riscv-debug-dtm | neorv32-setups | |
|---|---|---|
| 3 | 5 | |
| 12 | 53 | |
| - | - | |
| 0.0 | 8.6 | |
| over 1 year ago | 3 days ago | |
| VHDL | VHDL | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
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riscv-debug-dtm
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Input to FPGA
Here is a link to a JTAG Transport Module and some instructions how to read/write data words using OpenOCD: https://github.com/stnolting/riscv-debug-dtm
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Looking for feedback on my most recent project (anything welcome)
just a brief readme: https://github.com/stnolting/riscv-debug-dtm
- Confused about the JTAG interface
neorv32-setups
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How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.
- RISC-V with AXI Peripheral
- Open-source RISC-V CPU projects for contribution
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A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
and by "all" you of course mean some small Cyclones, Lattice ICE40s and Artix7 (see here)
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Risc-v rv32i softcore processor for Zybo-z7-10
There are some example setups here: https://github.com/stnolting/neorv32-setups
What are some alternatives?
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
litex - Build your hardware, easily!
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
neorv32-riscof - ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
fpu - IEEE 754 floating point library in system-verilog and vhdl
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
ORCA-risc-v - RISC-V by VectorBlox