cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux (by openhwgroup)
| cheshire | cva6 | |
|---|---|---|
| 1 | 10 | |
| 107 | 2,089 | |
| 10.3% | 2.2% | |
| 7.6 | 9.7 | |
| 3 days ago | 7 days ago | |
| SystemVerilog | Assembly | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
cheshire
Posts with mentions or reviews of cheshire.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-08.
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Cpu project
If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here
cva6
Posts with mentions or reviews of cva6.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-08.
- CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux
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Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
- The CORE-V CVA6 is a RISC-V CPU capable of booting Linux
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Capital required to design and manufacture smartphones/computers in US
There are 108 RISC-V cores that have been created so far (according to this list), but only a couple are 64 bit, open source and powerful enough that you would want to use them (like Shakti, CVA6 and NutShell)
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Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.
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Some data points on Vivado performance on Ryzen and Alder Lake
I made a post about this here not too long ago, but I think it would be really useful to come up with a Vivado benchmark, in the form of a standardized large and representative design. I was curious about Alder Lake performance too, and compared my new 12700K workstation against my laptop with this open source RISC-V CPU: https://github.com/openhwgroup/cva6
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What is Purism's roadmap for open-source hardware/schematics?
When the OpenHW Group was created in 2019, I had some hope that Alibaba or NXP (who are in the OpenHW Group) would release an open hardware RISC-V processor, but it looks like they are not making any public commits to the CVA6 core, so I doubt that we are ever going to see the source code of Alibaba's XT910 or NXP's Chassis RISC-V processor.
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XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76
Ariane is now cva6 (it moved to a industry supported non-profit).
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How many more years until we have a completely open source RISC-V SOC?
At this stage, it could make sense for e.g. universities to start developing peripherals & controllers targeted at ASIC rather than creating yet-another-core (https://riscv.org/exchange/cores-socs/ has 107 lines already for cores), leveraging an OSHW ASIC-proven core from e.g. the OpenHW group (https://github.com/openhwgroup/cva6). Manufacturing in not-so-old processes is affordable for teaching institutions (e.g. https://europractice-ic.com/ in Europe), and taping out working cores is no longer a 'new' thing (e.g. http://asic.ethz.ch/all/years.html ).
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OpenHW Group and Mitacs announce a $22.5M research program for open-source processors
Looking at the github of the openhw group looks like the license is granting patents to the project. So it looks ok.
What are some alternatives?
When comparing cheshire and cva6 you can also consider the following projects:
hdmi - Send video/audio over HDMI on an FPGA
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
friscv - RISCV CPU implementation in SystemVerilog
litex - Build your hardware, easily!
pulpissimo - This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
verilator - Verilator open-source SystemVerilog simulator and lint system
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
libsv - An open source, parameterized SystemVerilog digital hardware IP library
riscv_vhdl - Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
litedram - Small footprint and configurable DRAM core