openc906
rocket-chip
openc906 | rocket-chip | |
---|---|---|
14 | 12 | |
285 | 3,011 | |
1.1% | 1.0% | |
1.3 | 7.8 | |
12 months ago | 7 days ago | |
Verilog | Scala | |
Apache License 2.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
openc906
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Milk-V Duo: A $9 RISC-V COMPUTER
Datasheet: https://github.com/milkv-duo/hardware
Reading the datasheet, it looks like there is one C906 cpu with 700 Mhz without the the vector extension and one C906 cpu at 1Ghz with rvv 0.7.1. The C906 design has been opensourced and is available here: https://github.com/T-head-Semi/openc906
The C906 supports rv64gc with optimal rvv 0.7.1 with a vlen of 128, but a 256 wide ALU.
They list H.264/H.265 support, but I don't think it's a standardized extension.
But see my other comment about using the pre ratification vector extension:
- New RISC-V SoCs. Are they private and secure, or just more of the same?
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ARM versus RISC-V
Note that the implementations themselves are often not open source, for example a random person won't be able to get the sources of these SiFive cores anywhere. As of a open-source core from a commercial company, the OpenC906 is an open-source implementation provided by T-Head, but the vector unit is not included in the open source version and thus cannot enabled.
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Core2Duo doesnt have backdoor
Still not free hardware, real chads use XuanTie C906 based MangoPi MQ-PRO!
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Google wants RISC-V to be a “tier-1” Android architecture
Try and see if you can find any stolen code here[0] or here[1].
Cheers.
0. https://github.com/T-head-Semi/openc906
1. https://github.com/T-head-Semi/openc910
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RISC-V Pushes into the Mainstream
I wouldn't quite say that's the case. Two of the three full Linux capable RISC-V SoC releases this year are using open source CPU cores. The BL808 and the Allwinner D1 both use T-Head CPU cores that are available on GitHub https://github.com/T-head-Semi/openc906 . The JH7110 in the VisionFive2 and Star 64 does use a closed CPU core however.
- Store access fault when executing AMO instructions in Nezha D1
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Does a truly secure Linux system exist?
For example, let's take the ClockworkPi uConsole. It uses an Allwinner D1 chip as it's main processor which has a seemingly auditable XuanTie C906 which could theoretically be verified if one opened up a few chips.
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Buying RISC-V development board
For an example of what CPU core RTL looks like look no further than: https://github.com/T-head-Semi/openc906
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Packed-SIMD (P) vs Vector (V) extension
For example, for the record, the open source C906 RTL, found here https://github.com/T-head-Semi/openc906 doesn't even have the vector files in there.
rocket-chip
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Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
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RISC-V Pushes into the Mainstream
You could do a trial build of an in-order Rocket RISC-V core [1] to see how much space it takes up.
[1] https://github.com/chipsalliance/rocket-chip
- Can anyone explain simply how OpenSource the RISC-V actually is?
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Stages of prototyping a RISC-V processor on an FPGA?
My definition of a RISC CPU is one that has a reduced instruction set. In other words, the category of CPU is defined by the size of the instruction set, not in how it is implemented. Consider for example RISC-V CPUs. These are defined by their open instruction set alone, in spite of the fact that many implementations of RISC-V CPUs exist: some pipelined, and some not.
- FPGA for RISC-V Processor
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How are modern processors and their architecture designed?
More complex CPUs are typically completely out of scope for hand coding, therefore you can implement generators like: https://github.com/chipsalliance/rocket-chip
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
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Project ideas for RISC-V?
This would allow you to experiment with your own chip or something like [the RocketChip generator](https://github.com/chipsalliance/rocket-chip).
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Question: Does the 32bit version of Rocket still supports FPU
https://github.com/chipsalliance/rocket-chip/blob/c7da610430f51b02ebda37f3d444674dc8f2adbf/src/main/scala/system/Configs.scala#L28
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The First Affordable RISC-V Computer Designed to Run Linux
I don't know about the u74 specifically, but sifive does seem to invest in a open source risc-v core called rocket-chip.
What are some alternatives?
openc910 - OpenXuantie - OpenC910 Core
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
aosp-riscv - Patches & Script for AOSP to run on Xuantie RISC-V CPU [Moved to: https://github.com/T-head-Semi/riscv-aosp]
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
xuantie-yocto - Yocto project for Xuantie RISC-V CPU
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
riscv-profiles - RISC-V Architecture Profiles
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
riscv-aosp - Patches & Script for AOSP to run on Xuantie RISC-V CPU
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
linux - Patches include sunxi platform support and various driver fixes
Cores-VeeR-EH1 - VeeR EH1 core