openc906 VS riscv-isa-sim

Compare openc906 vs riscv-isa-sim and see what are their differences.

openc906

OpenXuantie - OpenC906 Core (by XUANTIE-RV)

riscv-isa-sim

Spike, a RISC-V ISA Simulator (by riscv-software-src)
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openc906 riscv-isa-sim
14 15
322 2,422
2.2% 1.8%
3.4 9.5
4 months ago 3 days ago
Verilog C
Apache License 2.0 GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

openc906

Posts with mentions or reviews of openc906. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-06-17.
  • Milk-V Duo: A $9 RISC-V COMPUTER
    4 projects | news.ycombinator.com | 17 Jun 2023
    Datasheet: https://github.com/milkv-duo/hardware

    Reading the datasheet, it looks like there is one C906 cpu with 700 Mhz without the the vector extension and one C906 cpu at 1Ghz with rvv 0.7.1. The C906 design has been opensourced and is available here: https://github.com/T-head-Semi/openc906

    The C906 supports rv64gc with optimal rvv 0.7.1 with a vlen of 128, but a 256 wide ALU.

    They list H.264/H.265 support, but I don't think it's a standardized extension.

    But see my other comment about using the pre ratification vector extension:

  • New RISC-V SoCs. Are they private and secure, or just more of the same?
    1 project | /r/privacy | 27 Apr 2023
  • ARM versus RISC-V
    2 projects | /r/RISCV | 9 Mar 2023
    Note that the implementations themselves are often not open source, for example a random person won't be able to get the sources of these SiFive cores anywhere. As of a open-source core from a commercial company, the OpenC906 is an open-source implementation provided by T-Head, but the vector unit is not included in the open source version and thus cannot enabled.
  • Core2Duo doesnt have backdoor
    2 projects | /r/linuxmemes | 27 Jan 2023
    Still not free hardware, real chads use XuanTie C906 based MangoPi MQ-PRO!
  • Google wants RISC-V to be a “tier-1” Android architecture
    2 projects | news.ycombinator.com | 3 Jan 2023
    Try and see if you can find any stolen code here[0] or here[1].

    Cheers.

    0. https://github.com/T-head-Semi/openc906

    1. https://github.com/T-head-Semi/openc910

  • RISC-V Pushes into the Mainstream
    5 projects | news.ycombinator.com | 23 Dec 2022
    I wouldn't quite say that's the case. Two of the three full Linux capable RISC-V SoC releases this year are using open source CPU cores. The BL808 and the Allwinner D1 both use T-Head CPU cores that are available on GitHub https://github.com/T-head-Semi/openc906 . The JH7110 in the VisionFive2 and Star 64 does use a closed CPU core however.
  • Store access fault when executing AMO instructions in Nezha D1
    1 project | /r/RISCV | 20 Dec 2022
  • Does a truly secure Linux system exist?
    2 projects | /r/RISCV | 13 Nov 2022
    For example, let's take the ClockworkPi uConsole. It uses an Allwinner D1 chip as it's main processor which has a seemingly auditable XuanTie C906 which could theoretically be verified if one opened up a few chips.
  • Buying RISC-V development board
    2 projects | /r/RISCV | 10 Nov 2022
    For an example of what CPU core RTL looks like look no further than: https://github.com/T-head-Semi/openc906
  • Packed-SIMD (P) vs Vector (V) extension
    1 project | /r/RISCV | 25 Oct 2022
    For example, for the record, the open source C906 RTL, found here https://github.com/T-head-Semi/openc906 doesn't even have the vector files in there.

riscv-isa-sim

Posts with mentions or reviews of riscv-isa-sim. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-12-10.

What are some alternatives?

When comparing openc906 and riscv-isa-sim you can also consider the following projects:

openc910 - OpenXuantie - OpenC910 Core

riscv-arch-test

aosp-riscv - Patches & Script for AOSP to run on Xuantie RISC-V CPU [Moved to: https://github.com/T-head-Semi/riscv-aosp]

sail-riscv - Sail RISC-V model

xuantie-yocto - Yocto project for Xuantie RISC-V CPU

rvv-intrinsic-doc

riscv-profiles - RISC-V Architecture Profiles

nanoCH32V305

riscv-aosp - Patches & Script for AOSP to run on Xuantie RISC-V CPU

qemu

vroom - VRoom! RISC-V CPU

jailhouse - Linux-based partitioning hypervisor

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