nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen (by m-labs)
XilinxVirtualCable
Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable. (by Xilinx)
nmigen | XilinxVirtualCable | |
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3 | 1 | |
643 | 186 | |
1.2% | 2.2% | |
1.8 | 5.3 | |
over 2 years ago | 30 days ago | |
Python | C | |
GNU General Public License v3.0 or later | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
nmigen
Posts with mentions or reviews of nmigen.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-07.
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Help a newbie
You can either decide to learn VHDL/Verilog, or use something like nmigen. I recommend learning either Verilog or VHDL anyway, so you can at least read and understand existing designs, but I personally use nmigen.
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Do these work as JTAG programmers?
Alternatively, you can just use Vivado to build the bitstream and then use alternative tools like https://github.com/trabucayre/openFPGALoader and http://xc3sprog.sourceforge.net/ to upload the bitstream to your FPGA. This is what I do since I use nmigen myself.
- How to compare HDL simulation/implementation results to Matlab?
XilinxVirtualCable
Posts with mentions or reviews of XilinxVirtualCable.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-07.
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Do these work as JTAG programmers?
Yes, any board with the FTDI FT232H works as a JTAG programmer (I actually have the one you linked). You may probably need some jumper wires that have the Xilinx-specific 0.2mm pitch, though, rather than the more convential 0.254mm or 0.1" pitch, if your FPGA board has the actual Xilinx JTAG header. To get it to work inside Vivado, you can use Xilinx Virtual Cable, which is a TCP/IP protocol to act as a JTAG cable (see https://github.com/Xilinx/XilinxVirtualCable and https://github.com/tmbinc/xvcd). The idea is that you basically have a TCP/IP daemon that speaks XVC and relies on libftdi or libusb to communicate with Vivado through XVC and do the actual JTAG programming.
What are some alternatives?
When comparing nmigen and XilinxVirtualCable you can also consider the following projects:
myhdl - The MyHDL development repository
XVC-FTDI-JTAG - Xilinx virtual cable server for generic FTDI 4232H.
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
xvcd - Xilinx Virtual Cable Daemon
pyverilator - Python wrapper for verilator model
openFPGALoader - Universal utility for programming FPGA
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
conifer - Collect and revisit web pages.