mrisc32-a1
fpu-sp
mrisc32-a1 | fpu-sp | |
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3 | 3 | |
22 | 21 | |
- | - | |
0.0 | 6.9 | |
8 months ago | 2 months ago | |
VHDL | VHDL | |
- | Apache License 2.0 |
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mrisc32-a1
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Got any good reads on floating point math design?
I saw a particularly efficient VHDL implementation in the mrisc32-a1, though this is lacking support for rounding modes. Together with the rest of the processor this is a very interesting project, I hope that the author progresses it further.
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Find the leading '0' Verilog question
Here is a different more logic gate:ish solution (in VHDL): https://github.com/mrisc32/mrisc32-a1/blob/master/rtl/alu/clz32.vhd
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Floating point unit in systemc
In my VHDL implementation I use the same iterative divider for integer and for floating-point: https://github.com/mrisc32/mrisc32-a1/blob/master/rtl/muldiv/div_impl.vhd
fpu-sp
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Intel discontinues Nios II IP
My team has a solution in place already, which was to write all of our floating point code to call macros rather than putting arithmetic in the code. This allowed us to port easily to an RV32IM CPU (a fork of this one) then memory map an FPU onto it, the macros were then changed to atomically access the FPU registers for any floating point arithmetic. In Intel chips we are using the Nios II floating point hardware 2 (which can be instantiated separately), in other vendors we use a combination of operators from the Opencores FPU and this one, depending upon what operators are selected via generics, the maths library will pick up what configuration is used and choose the available operators.
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High level floating point arithmetic in vhdl
Another really nice one that I found recently, uses a fused multiply add unit rather than seperate multiplier and adder. It's available in both mixed precision (double/single) and single precision flavours.
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Got any good reads on floating point math design?
I recently saw an interesting idea in this VHDL repository which combines addition and multiplication in a single fused multiply add unit. Division and square root are combined as well. In my opinion the FMADD block needs some more pipeline stages.
What are some alternatives?
cvfpu - Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
fpu - IEEE 754 floating point library in system-verilog and vhdl
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
or1200 - OpenRISC 1200 implementation
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
Hastlayer-SDK - Turning .NET software into FPGA hardware for faster execution and lower power usage.
hlsVHDL_floating_point
VHDL-Guide - VHDL Guide
edalize - An abstraction library for interfacing EDA tools