mrisc32-a1
forth-cpu
| mrisc32-a1 | forth-cpu | |
|---|---|---|
| 3 | 2 | |
| 22 | 315 | |
| - | - | |
| 0.0 | 2.6 | |
| 8 months ago | about 2 years ago | |
| VHDL | VHDL | |
| - | - |
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mrisc32-a1
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Got any good reads on floating point math design?
I saw a particularly efficient VHDL implementation in the mrisc32-a1, though this is lacking support for rounding modes. Together with the rest of the processor this is a very interesting project, I hope that the author progresses it further.
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Find the leading '0' Verilog question
Here is a different more logic gate:ish solution (in VHDL): https://github.com/mrisc32/mrisc32-a1/blob/master/rtl/alu/clz32.vhd
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Floating point unit in systemc
In my VHDL implementation I use the same iterative divider for integer and for floating-point: https://github.com/mrisc32/mrisc32-a1/blob/master/rtl/muldiv/div_impl.vhd
forth-cpu
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Designs targeting specific boards?
Like in my head I thought having a piece of verilog and having enough LUTs in any board would do the thing, so what meant here? An example https://github.com/howerj/forth-cpu mentions that the target board is a specific Xilinx.
- Forth SoC Written in VHDL
What are some alternatives?
cvfpu - Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
fpu-sp - IEEE 754 floating point library in system-verilog and vhdl
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga-toolchain - Multi-platform nightly builds of open source FPGA tools
hlsVHDL_floating_point
sdram-fpga - A FPGA core for a simple SDRAM controller.
fpga-fft - A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
VHDL-Guide - VHDL Guide