mrisc32-a1 VS fpu-sp

I saw a particularly efficient VHDL implementation in the mrisc32-a1, though this is lacking support for rounding modes. Together with the rest of the processor this is a very interesting project, I hope that the author progresses it further.

Here is a different more logic gate:ish solution (in VHDL): https://github.com/mrisc32/mrisc32-a1/blob/master/rtl/alu/clz32.vhd

In my VHDL implementation I use the same iterative divider for integer and for floating-point: https://github.com/mrisc32/mrisc32-a1/blob/master/rtl/muldiv/div_impl.vhd

My team has a solution in place already, which was to write all of our floating point code to call macros rather than putting arithmetic in the code. This allowed us to port easily to an RV32IM CPU (a fork of this one) then memory map an FPU onto it, the macros were then changed to atomically access the FPU registers for any floating point arithmetic. In Intel chips we are using the Nios II floating point hardware 2 (which can be instantiated separately), in other vendors we use a combination of operators from the Opencores FPU and this one, depending upon what operators are selected via generics, the maths library will pick up what configuration is used and choose the available operators.

Another really nice one that I found recently, uses a fused multiply add unit rather than seperate multiplier and adder. It's available in both mixed precision (double/single) and single precision flavours.

I recently saw an interesting idea in this VHDL repository which combines addition and multiplication in a single fused multiply add unit. Division and square root are combined as well. In my opinion the FMADD block needs some more pipeline stages.