icicle
edalize
icicle | edalize | |
---|---|---|
1 | 4 | |
284 | 593 | |
- | - | |
6.0 | 7.2 | |
12 months ago | 6 days ago | |
Python | Python | |
ISC License | BSD 2-clause "Simplified" License |
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icicle
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"AMD Extends the UltraScale+ Product Portfolio"
If you just need a system to practice VHDL / Verilog on, the $50 entry point is a bit better. It won't be fast or big, but there's plenty to do and learn on something like that. The ICE40 is large enough to get a RISCV core for example.
edalize
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Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
[1]: https://github.com/olofk/edalize
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
What are some alternatives?
kianRiscV - RISC-V Linux SoC, marchID: 0x2b
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
apio - :seedling: Open source ecosystem for open FPGA boards
icestudio - :snowflake: Visual editor for open FPGA boards
rggen - Code generation tool for control and status registers
sphinx-vhdl
opentitan - OpenTitan: Open source silicon root of trust
hdl_checker - Repurposing existing HDL tools to help writing better code
serv - SERV - The SErial RISC-V CPU
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.