gf180mcu-pdk
open-register-design-tool
| gf180mcu-pdk | open-register-design-tool | |
|---|---|---|
| 2 | 2 | |
| 338 | 182 | |
| 1.5% | 1.6% | |
| 2.8 | 5.3 | |
| 11 months ago | 9 months ago | |
| Makefile | Verilog | |
| Apache License 2.0 | Apache License 2.0 |
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gf180mcu-pdk
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Exploded view of my first ASIC, inside the TinyTapeout project
Google just committed to open sourcing the SKY90FD (formerly MITLL's 90nm FDSOI) and GF180MCU processes as well. So there's growing momentum in the open source PDK space.
- GlobalFoundries GF180MCU Open Source PDK
open-register-design-tool
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Thoughts about SystemRDL ?
I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
- Auto Generate Header Files
What are some alternatives?
rggen - Code generation tool for control and status registers
chipignite-resources
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
sky90fd-pdk
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
biriscv - 32-bit Superscalar RISC-V CPU
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication