gf180mcu-pdk
rggen
| gf180mcu-pdk | rggen | |
|---|---|---|
| 2 | 3 | |
| 337 | 279 | |
| 1.2% | 1.8% | |
| 2.8 | 7.7 | |
| 11 months ago | 3 months ago | |
| Makefile | Ruby | |
| Apache License 2.0 | MIT License |
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gf180mcu-pdk
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Exploded view of my first ASIC, inside the TinyTapeout project
Google just committed to open sourcing the SKY90FD (formerly MITLL's 90nm FDSOI) and GF180MCU processes as well. So there's growing momentum in the open source PDK space.
- GlobalFoundries GF180MCU Open Source PDK
rggen
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RgGen v0.28.0
I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
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RgGen update (support C header file generation)
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
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RgGen update
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
What are some alternatives?
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
chipignite-resources
sky90fd-pdk
PeakRDL-ipxact - Import and export IP-XACT XML register models
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
edalize - An abstraction library for interfacing EDA tools
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4