RISCV VS spu32

Compare RISCV vs spu32 and see what are their differences.

RISCV

A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i] (by georgeyhere)
risc-v Verilog Fpga

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spu32

Small Processing Unit 32: A compact RV32I CPU written in Verilog (by maikmerten)
risc-v risc-processor Fpga Verilog system-on-chip ice40 Rv32i icestorm
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RISCV spu32
1 1
11 60
- -
8.8 0.0
over 2 years ago almost 2 years ago
C C
- MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

RISCV

Posts with mentions or reviews of RISCV. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-22.
  • Novice needs help with RISC-V toolchain
    2 projects | /r/RISCV | 22 Jun 2021
    To this end, I wrote a testbench that encodes instructions and places them into a text file using SV structs. Is there any tool that can decode the output to Assembly instructions to check that the testbench is working? Or even better, is there some way to generate hex/binary code from Assembly? I have manually converted some instructions to binary and am reasonably sure the code works but am not 100% sure.

spu32

Posts with mentions or reviews of spu32. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-05-10.
  • Designing instruction decoder
    2 projects | /r/FPGA | 10 May 2021
    You asked for "elegant and simple". Disregarding your request, here's how I decode RISC-V: https://github.com/maikmerten/spu32/blob/master/cpu/decoder.v

What are some alternatives?

When comparing RISCV and spu32 you can also consider the following projects:

bronzebeard - Minimal assembler and ecosystem for bare-metal RISC-V development

shecc - A self-hosting and educational C optimizing compiler

NyuziProcessor - GPGPU microprocessor architecture

quasiSoC - No-MMU Linux capable RISC-V SoC designed to be useful.

openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

SAP1 - RTL Implementation of Malvino's SAP1. I was inspired to do this after seeing Ben Eater's Breadboard implementation

RISCV vs bronzebeard spu32 vs shecc RISCV vs NyuziProcessor spu32 vs quasiSoC RISCV vs openwifi spu32 vs Toast-RV32i RISCV vs quasiSoC spu32 vs esp RISCV vs Toast-RV32i spu32 vs cariboulite spu32 vs darkriscv spu32 vs SAP1