fpga-fft
vunit
fpga-fft | vunit | |
---|---|---|
1 | 10 | |
87 | 684 | |
- | 1.2% | |
0.0 | 8.2 | |
about 3 years ago | about 1 month ago | |
VHDL | VHDL | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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fpga-fft
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FPGA with DSP - which board and which FREE(!) software? 1M/s , 24bit FFT, FFT Ip?
Also, what is a small FFT for you? If I recall right the Xilinx FFT core is up to 2^16.. If you want to make a bigger FFT you need to divide it in little FFTs like this algorithm https://github.com/owocomm-0/fpga-fft
vunit
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Software languages vs HDLs for verification
My goto tools for verification in VHDL are UVVM and VUnit
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Libero - Inefficient Simulations
I think the VUnit vivado example (https://github.com/VUnit/vunit/tree/master/examples/vhdl/vivado) may be a good starting point when working with Xilinx IP outside of an IDE.
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Books About Testing and Verification
I learned a lot from https://vunit.github.io/ I even became a better VHDL engineer from this fantastic project. It showed me things I did not know VHDL was capable of.
- A couple of questions for the experts
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Reference of verification IPs
Hey! I haven't seen anyone mention Vunit yet. Vunit has a verification components library with Master and Slave components for a decent amount of buses: Axi, Axi stream, Wishbone, Avalon, Uart. The code isn't 100% bullet proof but it is really useful for testing designs.
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SystemVerilog testbench library
I agree vunit is great but due to circumstances (you can see post above) I need the testbench to be purely SV (and vunit as you said wouldn't help with all of that, only some of it, as you have pointed out). When I refered to vunit I forgot to link the example: https://github.com/VUnit/vunit/tree/master/examples/verilog/uart/src . I referred more to tge fact it is self checking, and the tasks can be reused in ither tbs as well
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The Vivado 2021.2 is out thread
As for simulation, the last time I used it there were a lot of features not supported. Not sure where this is documented, but I know VUnit can't support it per https://github.com/VUnit/vunit/issues/209 .
- How do you do automated testing of your HDL?
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VHDL Testbench Library Comparison
Please consider adding simulator support to this comparison. For example, Vivado's xsim can't be used with VUnit.
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The simplest way to automate my testbench?
I think these two examples can help you get started. https://github.com/VUnit/vunit/tree/master/examples/vhdl/array_axis_vcs https://github.com/VUnit/vunit/tree/master/examples/vhdl/generate_tests/
What are some alternatives?
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
DSP - Digital Signal Processing Library for Xilinx Platforms. Digital IIR/FIR filters, GHz rate non-linear pulse fitting, and data acquisition systems.
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
SoC - Github Repo for Embedded FPGA course by Vincent Claes
ghdl - VHDL 2008/93/87 simulator
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
fpga_torture - 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.