esp
spu32
| esp | spu32 | |
|---|---|---|
| 1 | 1 | |
| 297 | 60 | |
| 2.0% | - | |
| 7.5 | 0.0 | |
| 24 days ago | almost 2 years ago | |
| C | C | |
| GNU General Public License v3.0 or later | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
esp
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Looking for some FPGA projects on GitHub for Vitis /AI /HLS
Some pointers on GitHub: - Xilinx Vitis Tutorials (including HLS accelerators). - Basic Vitis HLS examples - Using Xilinx PYNQ board - ESP platform
spu32
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Designing instruction decoder
You asked for "elegant and simple". Disregarding your request, here's how I decode RISC-V: https://github.com/maikmerten/spu32/blob/master/cpu/decoder.v
What are some alternatives?
ara - The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
shecc - A self-hosting and educational C optimizing compiler
rosetta - Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
Vitis-HLS-Introductory-Examples
quasiSoC - No-MMU Linux capable RISC-V SoC designed to be useful.
Vitis-Tutorials - Vitis In-Depth Tutorials
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
litex - Build your hardware, easily!
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!