de10-nano VS litex

All signals are by default internal in qsys if you don't explicitly export them. So, if you want something out of the FPGA e.g. GPIO/LED you must export them. The column named export in qsys makes the signals appear in input/output ports of the module instance so that you can put them in top module i/o and assign pin locations using assignment editor. Partially explained here: https://github.com/zangman/de10-nano/blob/eef52965cba1386c441b738010e149589b8a0ed5/docs/Simple-Hardware-Adder_-Wiring-the-components.md

The Absolute Beginner's guide to DE10NANO (https://github.com/zangman/de10-nano/wiki for those who don't know) does have all the information you need for the fpga side.

what kind of help do you need? Given the wording, I guess you are talking about intel FPGAs. In that case, this is a nice guide even if you don't have that specific board: https://github.com/zangman/de10-nano/wiki

Anyways, feel free to just download and use the debian and archlinux images, perhaps you may still find them useful :).

Btw - just noticed you're using the de10-nano. In case you want to learn more about the SoC side of things, I have an absolute beginner's guide here - https://github.com/zangman/de10-nano/wiki. It walks you through the steps to building your own linux OS and writing your first HPS to FPGA project.

About a year ago, I published my wiki on the "Absolute beginner's guide to DE10-Nano". Here is the reddit post I made back then detailing all the topics covered (Build your own Debian OS, setting up dev environment etc).

https://github.com/enjoy-digital/litex

they have tutorials, you can get compatible boards for around $20

With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.

LiteX is a great example of a Python-first flow. However, they have chosen not to subordinate the scripting environment to a GUI toolchain - EDA vendors are unlikely to choose the same trade.

To lean these: https://github.com/enjoy-digital/litex, https://github.com/m-labs/migen

If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.

I am interested in trying out FPGAs for the purpose of running specific calculations more efficiently. Since the calculations themselves are quite complex, I would need to be able to program in a relatively high-level language. I've seen that designing SoC in Python is possible, for example with Litex (https://github.com/enjoy-digital/litex) or Amaranth (https://github.com/amaranth-lang/). I don't want to spend hundreds of hours learning about FPGAs, but I'm prepared to take on a challenge.