completor.vim
hdl_checker
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| completor.vim | hdl_checker | |
|---|---|---|
| 2 | 4 | |
| 1,225 | 183 | |
| - | - | |
| 0.0 | 0.0 | |
| about 2 months ago | 4 months ago | |
| Python | Python | |
| MIT License | GNU General Public License v3.0 only |
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completor.vim
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Omnicompletion sucks with the cursor on the end
completor
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Vim is amazing
When I recently started writing in Rust, I installed a few LSP related stuff and a completer. Try https://github.com/maralla/completor.vim ('maralla/completor.vim'), and you need "jedi" too for Python I think. I don't have it for Python installed, so don't know how well it works.
hdl_checker
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Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
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What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
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VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
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IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
What are some alternatives?
deoplete-jedi - deoplete.nvim source for Python
rust_hdl
YouCompleteMe - A code-completion engine for Vim
veridian - A SystemVerilog Language Server
coc.nvim - Nodejs extension host for vim & neovim, load extensions like VSCode and host language servers.
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
deoplete.nvim - :stars: Dark powered asynchronous completion framework for neovim/Vim8
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
ale - Check syntax in Vim/Neovim asynchronously and fix files, with Language Server Protocol (LSP) support
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
completion-nvim - A async completion framework aims to provide completion to neovim's built in LSP written in Lua
edalize - An abstraction library for interfacing EDA tools