autofpga
verilog-axi
autofpga | verilog-axi | |
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9 | 9 | |
156 | 1,267 | |
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4.3 | 3.0 | |
4 months ago | 5 months ago | |
C++ | Verilog | |
GNU General Public License v3.0 only | MIT License |
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autofpga
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How do you wire modules together?
I use AutoFPGA for connecting my top level components together. It handles bus composition and address assignment for me, while also creating linker, C header and Verilator simulation files for the project. Once a project is set up, reconfiguration is as easy as adding a file to the command line to add a component, or removing a file from the command line to remove a component. Make handles the rest.
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Tricks to make AXI wiring faster in Verilog?
I use AutoFPGA for all my bus connections. A single @$(SLAVE.PORTLIST) or @$(SLAVE.ANSPORTLIST) automatically expands into the connections required when instantiating a module. It'll also instantiate the crossbar for you as well.
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AXI InterConnect
Yes, I have posted an open source AXI interconnect. Unlike Xilinx's interconnect, mine doesn't automatically bridge between one bus width or clock and another, although some bridges exist in the same repository. Bridges exist, for example, for crossing clock domains, going from AXI3 to AXI4, from AXI4 to AXI4-lite, from AXI4 to a smaller AXI4-lite, and from AXI4-lite to a wider width. It's been enough to keep me from needing my own AXI4 interconnect, although AXI can be a real pain to wire up. As a result, I tend to use AutoFPGA for that purpose.
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Hey Xilinx users, let me have it...
Now, whether or not AutoFPGA fits the bill for anyone--that's an entirely different question. I suspect the answer is, "No", but that's really a different conversation for a different time/thread. One of the things it can do is compose an AXI bus from multiple master and slave configurations--all using user controlled and very version controllable configuration files. The big problem it has (currently) is the lack of a strong verification suite. That's probably going to hit the top of my to-do list soon enough.
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SoC FPGA design to ASIC
An SoC composer? You'll need something that takes multiple bus components and stitches them together. I've used AutoFPGA extensively for this purpose, and continue to do so today. It's biggest problem? I haven't put a lot of energy into marketing it, so the documentation is more lacking than I would like. Still, it's worked quite well for me and my intermediate tutorial (work in progress) provides some discussion of how to work with it.
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Tricks to make AXI wiring faster in Verilog
AutoFPGA can do simple bus line pattern substitution. For example, these two configuration lines then expand to these 65 lines.
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CPU DESIGN
There are also open source versions of many of the pieces you will need. I now use an open source crossbar interconnect for most of my designs. I use AutoFPGA to connect all the pieces together. I mentioned my flash controller above, but I also have a SD Card controller I've used quite successfully. I've also posted a UART to Wishbone bridge and discussed network debugging, both of which I use routinely with the ZipCPU. If for no other reason, these components allow me to load or update software on my CPU even after it's been placed into an FPGA. Of course, many of those components are tied to a Wishbone bus infrastructure. You may find you need a bridge of some type to connect different buses structures together--memory naturally tends to operate at one width and clock, video at another, and your CPU at another, so it helps at times to have a universal bus adapter kit handy.
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Auto generate header files
I generated my own solution to this problem, a solution which I called AutoFPGA. It's not IP-XACT. It configures a design based upon a bus with (potentially) multiple masters and slaves. Configuration files are designed on a per-unit basis, with the intention that a slave (or master) configuration file could be removed to remove that portion of the design from the whole.
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FPGA and Simulation tools for Risc-V design
If you wish to build a SOC design, you'll need some approach to assembling the bus together. There will be a lot of wires to connect, and a lot of logic to build just to get you off the ground. You'll find several SOC based building tools out there to use. I've built my own, AutoFPGA, which I use for assembling peripherals around a CPU based design. You might find an open source crossbar interconnect to be quite valuable as well. I've built crossbars for AXI, AXI-lite, and Wishbone (pipeline). I know there's a good Wishbone classic crossbar out there as well, I just don't have the link at my fingertips. (Good? It'll slow down your overall clock speed, while yielding poorer performance compared to Wishbone pipeline--but that's just the reality of working with Wishbone classic.)
verilog-axi
- awready and wready set high in master without salve value · Issue #57 · alexforencich/verilog-axi
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Using Xilinx AXI interconnect to connect AXI lite master to AXI lite slaves
You can also use an AXI lite crossbar like this one: https://github.com/alexforencich/verilog-axi/blob/master/rtl/axil_crossbar.v
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OS AXI4 Crossbar with good performance
does anybody knows some sort of AXI4 Crossbar or maybe even an Interconnect with good performance in terms of latency? If I have something like the following scenario, the idea is that M1 txns must have very low access latency in the sense of making the CPU capable of processing at least one instruction per cc. For M2 it's fine to take more time, but what I'm observing is that with this solution for instance, I cannot achieve constant fetching from the CPU, there's always a 1 cc delay between req/resp what hits bad my IPC. Also, S1 cannot be tightly coupled to the CPU because sometimes M2 might require to also fetch from IRAM/ROM. Is it better to switch to another protocol to achieve such good performance latency? if so, what open source available solution can have interesting perf. num, wishbone / AHB?
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Hey Xilinx users, let me have it...
You can also look at some of my code, which is all MIT licensed: https://github.com/alexforencich/verilog-axi
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BRAM to AXI Stream in Xilinx Devices
AXI DMA, or the datamover core that the AXI DMA core uses internally, depending on your use case. I also have an open source AXI DMA module that's comparable to the Xilinx datamover core here: https://github.com/alexforencich/verilog-axi/blob/master/rtl/axi_dma.v
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Converting an FPGA design to ASIC
Xilinx soft IPs: I use the Xilinx IPs: AXI DMA, AXI-Stream Datawidth converter, AXI-Stream Clock converter...etc, for which I'm able to find open source RTL designs here, here and here.
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Fast, open-source RTL IPs for fixed & floating-point multiplication, accumulation & conversion
I'm thinking of synthesizing it with ASIC tools such as Synopsys DesignCompiler to check the area & timing. I found some open source projects with Verilog IPs for AXI (zipcpu, alexforencich) and AXIS (alexforencich) modules, and I think I can replace the Xilinx IPs with them. After publishing my paper, I'm planning to release my code as open-source as well.
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Assigning values to Verilog parameters from Cocotb?
Thanks for the reply! I ran a particular testbench from your repository but when I placed print statements(print(tb.dut.S_DATA_WIDTH.value) in each test (run_test_write,run_test_read) , I found that it prints out the default parameter value (32) every time.
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Can someone please explain to me the basic parts of a Cocotb testbench?
Here's one of my cocotb testbenches for reference: https://github.com/alexforencich/verilog-axi/blob/master/tb/axi_adapter/test_axi_adapter.py .
What are some alternatives?
riscv-arch-test
wb2axip - Bus bridges and other odds and ends
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
verilog-axis - Verilog AXI stream components for FPGA implementation
Rudi-RV32I - A rudimental RISCV CPU supporting RV32I instructions, in VHDL
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
axidmacheck - AXI DMA Check: A utility to measure DMA speeds in simulation
openarty - An Open Source configuration of the Arty platform
verilog-axi - Verilog AXI components for FPGA implementation
riscv-formal - RISC-V Formal Verification Framework
zipcpu - A small, light weight, RISC CPU soft core