amaranth
SpinalHDL
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amaranth | SpinalHDL | |
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7 | 8 | |
1,436 | 1,518 | |
4.2% | 3.2% | |
9.7 | 9.8 | |
6 days ago | 4 days ago | |
Python | Scala | |
BSD 2-clause "Simplified" License | GNU General Public License v3.0 or later |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
amaranth
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Why are there only 3 languages for FPGA development?
He probably meant Amaranth.
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VRoom A high end RISC-V implementation
As an aside, the latest and active development of nMigen has been rebranded a few months ago to Amaranth and can be found here: https://github.com/amaranth-lang/amaranth . In case people googled nMigen and came to the repository that hasn't been updated in two years.
- NMigen – A Python toolbox for building complex digital hardware (FPGAs)
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Facts every web dev should know before they burn out and turn to painting
Hmm. A followup question: are there any cheats/hacks that would make it possible (if painful) to for example explore the world of USB3, PCIe, or Linux on low-end-ish ARM (eg https://www.thirtythreeforty.net/posts/2019/12/my-business-c..., based on the 533MHz https://linux-sunxi.org/F1C100s), without needing to buy equipment in the mid-4-figure/low-5-figure range, if I were able to substitute a statistically larger-than-average amount of free time (and discipline)?
For example, I learned about https://github.com/GlasgowEmbedded/glasgow recently, a bit of a niche kitchen sink that uses https://github.com/nmigen/nmigen/ to lower a domain-specific subset of Python 3 (https://nmigen.info/nmigen/latest/lang.html) into Verilog which then runs on the Glasgow board's iCE40HX8K. The project basically makes it easier to use cheap FPGAs for rapid iteration. (The README makes a point that the synthesis is sufficiently fast that caching isn't needed.)
In certain extremely specific situations where circumstances align perfectly (caveat emptor), devices like this can sometimes present a temporary escape to the inevitable process of acquiring one's first second-hand high-end oscilloscope (fingers-crossed the expensive bits still have a few years left in them). To some extent they may also commoditize the exploration of very high-speed interfaces, which are rapidly becoming a commonplace principal of computers (eg, having 10Gbps everywhere when USB3.1 hits market saturation will be interesting) faster than test and analysis kit can keep up (eg to do proper hardware security analysis work). The Glasgow is perhaps not quite an answer to that entire statement, but maybe represents beginning steps in that sort of direction.
So, to reiterate - it's probably an unhelpfully broad question, and I'm still learning about the field so haven't quite got the preciseness I want yet, but I'm curious what gadgetry, techniques, etc would perhaps allow someone to "hack it" and dive into this stuff on a shoestring budget? :)
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Awesome Lattice FPGA Boards
Worth knowing that are two "nmigen"s nowadays - the one originated in M-Labs and one under a project also called nmigen:
https://github.com/nmigen/nmigen
It's a fork, made for reasons, but more actively developed. whitequark (long time author/contributor) works on this fork, and no longer the M-Labs version.
- Chisel/Firrtl Hardware Compiler Framework
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Unifying the CUDA Python Ecosystem
Sounds like nmigen might be a good open source successor to the project that you describe: https://github.com/nmigen/nmigen
SpinalHDL
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1800-2023 – IEEE Standard for SystemVerilog
I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be and also have a textual preprocessor defined internally. It doesn't work.
I really like what Zig and C++ are doing with `const`.
https://ikrima.dev/dev-notes/zig/zig-metaprogramming/
Have you looked at Spinal?
https://github.com/SpinalHDL/SpinalHDL
https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html
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Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.
If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.
[1] https://github.com/ucb-bar/chipyard
[2] https://github.com/SpinalHDL/SpinalHDL
[3] https://github.com/B-Lang-org/bsc
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Simple skid buffer implementation
I have just found that SpinalHDL also implemented two halves of the fully registered buffer in Stream.scala.
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Why are there only 3 languages for FPGA development?
Don’t forget SpinalHDL that was forked off of Chisel 2 I believe. These DSLs really leveraged the software features of Scala to help build generalised/modular systems. And are generally a quality of life improvement in the language features available.
- SpinalHDL – A high level hardware description language based on Scala
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
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Suggest advance project ideas
You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.
- Chisel/Firrtl Hardware Compiler Framework
What are some alternatives?
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
chisel - Chisel: A Modern Hardware Design Language
litex - Build your hardware, easily!
chiselverify - A dynamic verification library for Chisel.
myhdl - The MyHDL development repository
litepcie - Small footprint and configurable PCIe core
pygears - HW Design: A Functional Approach
circt - Circuit IR Compilers and Tools
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler