UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/ (by UVVM)
AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components (by OSVVM)
UVVM | AXI4 | |
---|---|---|
6 | 4 | |
328 | 103 | |
- | 6.8% | |
5.7 | 7.6 | |
11 days ago | 25 days ago | |
VHDL | VHDL | |
Apache License 2.0 | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
UVVM
Posts with mentions or reviews of UVVM.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-02-11.
-
Software languages vs HDLs for verification
Using the open source UVVM (Universal VHDL Verification Methodology) will allow you to write high level (transaction level) testbenches using commands like 'axistream_transmit(my_byte_array)'. UVVM includes a large range of open source interface access mechanisms like that (BFMs & Verification components) like AXI, AXI-lite, AXI-stream, Avalon, Avalon-stream, Ethernet, GMII, RGMII, I2C, SPI, SBI, UART, etc. You can check out my presentation from DVCon US 2022 on 'Bringing UVM to VHDL' to get an introduction to UVVM. There are also lots of different webinars available for free on various aspects of UVVM.
- Books About Testing and Verification
- Verilog Text Book Recommendations?
-
Getting Into Verification
I don't have enough experience to comment on what you should do, but I haven't seen UVVM mentioned in this thread, which is a testbench library for VHDL. It has a lot of nice functions for value checking and logging, as well as BFMs for SPI, UART, I2C, etc.
-
Using tool for HDL verification/simulation
UVVM is a good platform for VHDL testbenches.
AXI4
Posts with mentions or reviews of AXI4.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-02-02.
-
I made an AXI introduction video! including an AXI-Lite master read and write example!
OSVVM also has an AXI4 VC/VIP. See https://github.com/OSVVM/OsvvmLibraries and for AXI4 specifically see: https://github.com/OSVVM/Axi4
- Reference of verification IPs
- Verilog Text Book Recommendations?
-
Entity Input Ports
If you are looking for an AXI Subordinate (new AXI spec names) Memory, you may wish to look at the one from OSVVM (it is free open source (FOSS)). You will find it at: https://github.com/OSVVM/AXI4/blob/master/Axi4/src/Axi4Memory.vhd
What are some alternatives?
When comparing UVVM and AXI4 you can also consider the following projects:
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
vc_axi
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
rust_hdl
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
wb2axip - Bus bridges and other odds and ends
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.