AXI4
vc_axi
| AXI4 | vc_axi | |
|---|---|---|
| 4 | 1 | |
| 103 | 4 | |
| 5.0% | - | |
| 7.6 | 10.0 | |
| 22 days ago | almost 5 years ago | |
| VHDL | VHDL | |
| GNU General Public License v3.0 or later | - |
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AXI4
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I made an AXI introduction video! including an AXI-Lite master read and write example!
OSVVM also has an AXI4 VC/VIP. See https://github.com/OSVVM/OsvvmLibraries and for AXI4 specifically see: https://github.com/OSVVM/Axi4
- Reference of verification IPs
- Verilog Text Book Recommendations?
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Entity Input Ports
If you are looking for an AXI Subordinate (new AXI spec names) Memory, you may wish to look at the one from OSVVM (it is free open source (FOSS)). You will find it at: https://github.com/OSVVM/AXI4/blob/master/Axi4/src/Axi4Memory.vhd
vc_axi
What are some alternatives?
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
UVVM - UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
rust_hdl
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
wb2axip - Bus bridges and other odds and ends
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.