KinnowCPU
ApogeoRV
| KinnowCPU | ApogeoRV | |
|---|---|---|
| 1 | 1 | |
| 3 | 13 | |
| - | - | |
| 3.6 | 9.3 | |
| 10 months ago | about 2 months ago | |
| C | SystemVerilog | |
| - | MIT License |
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KinnowCPU
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Mintia: my paging operating system written in a custom language for a custom architecture
Someone did a verilog implementation of the instruction set, but it only gets to the boot rom prompt because they didn't implement the TLB. It's a cool long term goal for me to do a full system implementation in verilog or something, but I'm just one person and there's a lot to do, so I'm not sure I'll get around to that any time soon.
ApogeoRV
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Need help with B.tech last year project! On cache memory controller design using verilog hdl
I am designing a cache controller in SystemVerilog for my RISCV CPU, it's currently under verification so there are a lot of bugs, but you can take a look to the code (https://github.com/GabbedT/RV32-Apogeo/tree/main/Hardware/Memory%20System/Data%20Cache) and to the documentation (https://github.com/GabbedT/RV32-Apogeo/blob/main/Docs/data-cache.md) (not up to date). Take this just as an example because I'm simply a third year bachelor student and this is only a personal project (I'm not followed by a professor or anything like that) so it might not be the best way to implement a cache controller.
What are some alternatives?
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
mintia - Paging operating system for a custom computer architecture
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
NyuziProcessor - GPGPU microprocessor architecture
riscv - RISC-V CPU Core (RV32IM)
sdk - Cross-toolchain for XR/station programming
BrianHG-DDR3-Controller - DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
fox32 - fox32 virtual machine
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software