FPGA_RealTime_and_Static_Sobel_Edge_Detection
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images (by AngeloJacobo)
WARP_Core
Wilson AXI RISCV Processor Core (by AEW2015)
| FPGA_RealTime_and_Static_Sobel_Edge_Detection | WARP_Core | |
|---|---|---|
| 3 | 2 | |
| 36 | 7 | |
| - | - | |
| 0.0 | 0.0 | |
| over 2 years ago | almost 4 years ago | |
| Verilog | VHDL | |
| MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
FPGA_RealTime_and_Static_Sobel_Edge_Detection
Posts with mentions or reviews of FPGA_RealTime_and_Static_Sobel_Edge_Detection.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-09.
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Sobel edge detection
Hi, you might be interested on having a look at this project. The main RTL for the convolution is in sobel_convolution.v
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
I posted this project on this sub three weeks ago,
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Real-Time Sobel Edge Detection using FPGA (repo link in the comments)
Project repository
WARP_Core
Posts with mentions or reviews of WARP_Core.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-29.
-
Uploading software program to a custom processor design on a Nexys A7
HW: https://github.com/AEW2015/WARP_Core/blob/master/Projects/P_Test/Src/hdl/bscan_if.vhd
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
What are some alternatives?
When comparing FPGA_RealTime_and_Static_Sobel_Edge_Detection and WARP_Core you can also consider the following projects:
litex - Build your hardware, easily!
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
SpinalHDL - Scala based HDL
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
FPGA_OV7670_Camera_Interface - Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
fiate - Fault Injection Automatic Test Equipment
ULX3S_FPGA_Camera_Streaming - Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs litex
WARP_Core vs soft_riscv
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs SpinalHDL
WARP_Core vs verilog-ethernet
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs verilog-ethernet
WARP_Core vs SBusFPGA
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs FPGA_OV7670_Camera_Interface
WARP_Core vs SpinalHDL
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs SBusFPGA
WARP_Core vs fiate
FPGA_RealTime_and_Static_Sobel_Edge_Detection vs ULX3S_FPGA_Camera_Streaming
WARP_Core vs neorv32