Top 11 wishbone Open-Source Projects

zipcpu

13 1,190 6.3 Verilog

A small, light weight, RISC CPU soft core
wb2axip

51 431 3.1 Verilog

Bus bridges and other odds and ends
InfluxDB

www.influxdata.com sponsored

Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
wbuart32

4 250 4.6 Verilog

A simple, basic, formally verified UART controller

Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

sdspi

4 137 7.4 Verilog

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

openarty

6 116 0.0 Verilog

An Open Source configuration of the Arty platform

Project mention: C++ Verification Testbench Best-Practice Resources? | /r/FPGA | 2023-06-11

I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.

uart-for-fpga

1 84 0.0 VHDL

Simple UART controller for FPGA written in VHDL
wbscope

1 70 3.7 Verilog

A wishbone controlled scope for FPGA's
WorkOS

workos.com sponsored

The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
lxp32-cpu

2 55 0.0 Assembly

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
dbgbus

5 31 3.9 Verilog

A collection of debugging busses developed and presented at zipcpu.com
wbfmtx

1 19 2.8 Verilog

A wishbone controlled FM transmitter hack
wbicapetwo

2 8 0.0 Verilog

Wishbone to ICAPE interface conversion

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).