vscode-terosHDL VS hdl_checker

Compare vscode-terosHDL vs hdl_checker and see what are their differences.

vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more! (by TerosTechnology)
Verilog Vhdl Systemverilog Fpga
Source Code
terostechnology.github.io
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hdl_checker

Repurposing existing HDL tools to help writing better code (by suoto)
Vhdl modelsim Xilinx Verilog Systemverilog Python Hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl Vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
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vscode-terosHDL hdl_checker
3 4
510 184
6.1% -
9.2 0.0
about 11 hours ago 5 months ago
JavaScript Python
GNU General Public License v3.0 only GNU General Public License v3.0 only
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vscode-terosHDL

Posts with mentions or reviews of vscode-terosHDL. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-10-13.

hdl_checker

Posts with mentions or reviews of hdl_checker. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-02-23.
  • Any better options than Sigasi?
    2 projects | /r/FPGA | 23 Feb 2022
    I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
  • What Editor is Everyone Using for FPGA design? (2021)
    2 projects | /r/FPGA | 28 Jun 2021
    NeoVim + CoC + hdl_checker
  • VHDL native lsp
    1 project | /r/neovim | 24 Jun 2021
    As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
  • IDE / Editor of choice
    1 project | /r/FPGA | 19 Mar 2021
    Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.

What are some alternatives?

When comparing vscode-terosHDL and hdl_checker you can also consider the following projects:

rggen - Code generation tool for control and status registers

completor.vim - Async completion framework made ease.

vscode-terosHDL vs rggen hdl_checker vs completor.vim