trv
riscv-isa-sim
trv | riscv-isa-sim | |
---|---|---|
11 | 15 | |
8 | 2,218 | |
- | 3.0% | |
1.8 | 9.0 | |
over 3 years ago | 7 days ago | |
C | C | |
- | GNU General Public License v3.0 or later |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
trv
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RPython-based emulator speeds up RISC-V simulation over 15x
Spike is a pure interpreter -- no JIT or anything like that. It is written to be very portable, very easy to add new instructions to, and easy to reason about whether you have done it correctly. Essentially no effort is made to get high performance. Spike was the "Golden Standard" for RISC-V semantics until some academics said "that's not good enough, you should use Sail because formal this, proof that".
The only time the RISC-V instruction set should be changing is when new instructions are being added, and during the extension development process the set of instructions and meaning or especially the binary encoding of individual instructions can change.
I have been the person doing the modifications to Spike during development of RISC-V extensions, and in particular during a quite fluid stage of the development of the Vector extension. I know how easy it is to do this. Just as easy as Sail, I would say.
Here's one example of why.
Most RISC-V emulators decode instructions using a series of nested switch statements. Zeroth, switch on non-C vs which page of C (if C is implemented) bits 1:0. First switch on the "opcode" field bits 6:2 e.g. OP-IMM or LOAD or BRANCH. Second, typically, switch on the "funct3" field bits 14:12 which distinguishes e.g. ADD / SLT / SLTU / AND / OR / XOR / SLL / SRL for arithmetic instructions or BEQ / BNE / BLT / BLTU / BGE / BGEU for conditional branches, or operand size for loads and stores. Third, for some instructions switch on the "funct7" field bits 31:25 to distinguish between e.g. ADD / SUB or SRL / SRA.
This is pretty fast and efficient and makes compact code/tables, but it is high maintenance.
Spike decodes instructions with a loop searching a linear list of MASK and MATCH values until it finds the correct instruction. So, by the way, does my simple "trv" emulator.
Here is my own complete executable C definition of RV32I:
https://github.com/brucehoult/trv/blob/main/instructions.inc
The 3rd and 4th values (the hex ones) are the MATCH and MASK values. The logic is "if ((instruction & MASK) == MATCH)" for example:
if ((instruction & 0xfe00707f) == 0x40000033) rd = rs1 - rs2; // sub
- Top Ten Fallacies About RISC-V (David Patterson)
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Handy commands for using the RISC-V gnu toolchain and generate .elf or .hex w/ libgcc
bruce@rip:~$ git clone https://github.com/brucehoult/trv.git Cloning into 'trv'... remote: Enumerating objects: 10, done. remote: Counting objects: 100% (10/10), done. remote: Compressing objects: 100% (8/8), done. remote: Total 10 (delta 2), reused 10 (delta 2), pack-reused 0 Receiving objects: 100% (10/10), 4.37 KiB | 4.37 MiB/s, done. Resolving deltas: 100% (2/2), done. bruce@rip:~$ cd trv bruce@rip:~/trv$ gcc -O trv.c -o trv bruce@rip:~/trv$ cat >foo.s < .globl main > main: > li a0,3 > li a1,23 > call __mulsi3 > ret > END bruce@rip:~/trv$ riscv64-unknown-elf-gcc -O -march=rv32i -mabi=ilp32 foo.s -o foo bruce@rip:~/trv$ qemu-riscv32 foo bruce@rip:~/trv$ echo $? 69 bruce@rip:~/trv$ riscv64-unknown-elf-objcopy -O ihex foo foo.hex bruce@rip:~/trv$ ./trv foo.hex bruce@rip:~/trv$ echo $? 69
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Hardware/software to run RISC-V ASM?
I completely understand. I have a toy RV32I emulator myself at https://github.com/brucehoult/trv which desperately needs even a README. I want to do it, but I keep forgetting to do it...
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rvscript: Fast RISC-V-based scripting backend for game engines
I didn't see what actual emulator this uses, but I have a super-simple one (sadly undocumented but the code is short!) that runs Intel hex files at https://github.com/brucehoult/trv
- Why RISC-V Is Succeeding
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8-bit Breadboard Computer
The easiest way would be to get a C compiler for 6502 or z80 and compile a simple RISC-V emulator such as my one at https://github.com/brucehoult/trv
- Built a 65C02 emulator
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Linux in a Pixel Shader – A RISC-V Emulator for VRChat
If you're making the actual game, and can therefore implement the virtual machine in native code on the host machine (instead of in a shader on the GPU as here) then you can very easily get 10 to 100 MIPS performance in an emulated machine with a very simple emulator. Such as https://github.com/brucehoult/trv
Bear in mind that the original Mac was roughly a 2 MIPS machine and an early Pentium or PowerMac 100 MIPS.
- ELF binary executable format and sections.
riscv-isa-sim
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RISC-V simulator
Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.
- Help needed in building cavatools
- GCC 13 Adds RISC-V T-Head Vendor Extension Collection
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Hardware/software to run RISC-V ASM?
Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim
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most underrated cpp project you’ve seen?
I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.
- C++17 RISC-V RV32/64/128 userspace emulator library
- Buying RISC-V development board
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Is there a way to run RISCV sim spike on bare metal?
If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.
- switching between privilege levels
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
What are some alternatives?
ch32v307 - Including the SDK、HDK、Datasheet of RISC-V MCU CH32V307 and other relevant development materials
sail-riscv - Sail RISC-V model
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
riscv-arch-test
nanoCH32V305
rvv-intrinsic-doc
qemu
jailhouse - Linux-based partitioning hypervisor
riscv-none-elf-gcc-xpack - A binary distribution of the GNU RISC-V Embedded GCC toolchain
discreture - A modern C++ library for efficiently and easily iterating through common combinatorial objects, such as combinations, permutations, partitions and more.