spydrnet
naja
| spydrnet | naja | |
|---|---|---|
| 1 | 4 | |
| 85 | 42 | |
| - | - | |
| 6.8 | 9.0 | |
| 2 months ago | 7 days ago | |
| Python | Python | |
| BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
spydrnet
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Is there a minimal HDL?
Here is a python tool to modify netlist / edit files. https://github.com/byuccl/spydrnet
naja
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Naja-Verilog: stand-alone structural (gate-level) parser
Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
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Show HN: Naja-Verilog – Structural Verilog Parser
The project's other github repo is better to learn more about the project: https://github.com/xtofalex/naja
The linked repo doesn't have a informative Readme. An example showing showing Naja differs from existing tools would help people unfamiliar with Electronic Design Automation, like me.
- Naja - Open-source data structures for EDA back end tools development
- Show HN: Naja – open-source data structures for EDA back end tools development
What are some alternatives?
difw - Expressive diffeomorphic transformations based on the closed-form integration of continuous piecewise affine velocity functions.
naja-verilog - A standalone structural (gate-level) verilog parser
metron - A C++ to Verilog translation tool with some basic guarantees that your code will work.
stargan2 - StarGAN2 for practice
verilator - Verilator open-source SystemVerilog simulator and lint system
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
rggen - Code generation tool for control and status registers
OpenRAM - An open-source static random access memory (SRAM) compiler.
Beagle_SDR_GPS - KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
neorv32-verilog - ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
fpga_floorplanning - NTHU CS5160 FPGA結構及設計自動化 麥偉基 Final Project