simple-riscv
neorv32-setups
| simple-riscv | neorv32-setups | |
|---|---|---|
| 5 | 5 | |
| 19 | 53 | |
| - | - | |
| 2.7 | 8.6 | |
| about 3 years ago | 7 days ago | |
| VHDL | VHDL | |
| MIT License | BSD 3-clause "New" or "Revised" License |
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simple-riscv
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How to run DOOM on a custom-made CPU in VHDL
Have a look at https://github.com/hamsternz/simple-riscv/tree/main/sw for how I did this for my toy processor. In particular https://github.com/hamsternz/simple-riscv/tree/main/sw/image_to_mem does the heavy lifting.
- Running VIVADO project from batch- linux , by using tcl file.
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
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Is a single cycle CPU of any use besides learning?
If you want to see my ISA testing source have a look at: https://github.com/hamsternz/simple-riscv/blob/main/sw/asm/isa_test.S
neorv32-setups
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How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.
- RISC-V with AXI Peripheral
- Open-source RISC-V CPU projects for contribution
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A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
and by "all" you of course mean some small Cyclones, Lattice ICE40s and Artix7 (see here)
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Risc-v rv32i softcore processor for Zybo-z7-10
There are some example setups here: https://github.com/stnolting/neorv32-setups
What are some alternatives?
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
riscv-tests
litex - Build your hardware, easily!
riscv-formal - RISC-V Formal Verification Framework
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
fpu - IEEE 754 floating point library in system-verilog and vhdl
Cores-VeeR-EH1 - VeeR EH1 core
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine