satcat5
litex
| satcat5 | litex | |
|---|---|---|
| 25 | 29 | |
| 390 | 2,688 | |
| 10.5% | - | |
| 3.8 | 9.7 | |
| 2 months ago | 7 days ago | |
| VHDL | C | |
| CERN Open Hardware Licence Version 2 - Weakly Reciprocal | GNU General Public License v3.0 or later |
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satcat5
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Layout of Rust's u128 and i128 changed
I needed 128-bit and 256-bit integers on an embedded project recently.
In short, it was for fixed-point digital signal processing. The raw input and output samples were int64_t. We needed to add, subtract, multiply, and accumulate these to do filtering and linear regression with no loss of precision.
Conventional bigintegers weren't an option because the target application doesn't allow heap allocation. So we rolled our own [1] stack-allocated, fixed-width big integer class.
[1] https://github.com/the-aerospace-corporation/satcat5/blob/ma...
- Show HN: SatCat5, the open-source FPGA Ethernet switch
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CRC32 algorithm match value between 96 bit wide data bus and 24 bit wide data bus
And here's an open-source implementation I wrote a few years back. You can skip the part at the end that handles variable-length trailing bytes, since you have a fixed-width input.
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Questions about lattice ecp5 fpga.
My SatCat5 project also has a few options. Anything under src/vhdl/common/cfgbus_* can be connected to AXI or Wishbone with a simple adapter.
- SatCat5: FPGA gateware that implements a low-power, mixed-media Ethernet switch
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GPSDO without VCXO?
For an all-digital solution, here's an NCO that generates an arbitrary-frequency square wave from a numeric counter.
- network switch
litex
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FPGA Dev Boards for $150 or Less
https://github.com/enjoy-digital/litex
they have tutorials, you can get compatible boards for around $20
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Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
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Sunset TCL scripts ?
LiteX is a great example of a Python-first flow. However, they have chosen not to subordinate the scripting environment to a GUI toolchain - EDA vendors are unlikely to choose the same trade.
- synthesizing and using the Ibex RISC-V core
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Been messing around with litex and migen on my Tang Primer 20K
To lean these: https://github.com/enjoy-digital/litex, https://github.com/m-labs/migen
- CPU design for college project
- How can I learn about RISC-V and use case? I want to do a project for begginers
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.
- LiteX: Build Hardware Easily
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Using FPGAs for computations as a beginner
I am interested in trying out FPGAs for the purpose of running specific calculations more efficiently. Since the calculations themselves are quite complex, I would need to be able to program in a relatively high-level language. I've seen that designing SoC in Python is possible, for example with Litex (https://github.com/enjoy-digital/litex) or Amaranth (https://github.com/amaranth-lang/). I don't want to spend hundreds of hours learning about FPGAs, but I'm prepared to take on a challenge.
What are some alternatives?
verilog-ethernet - Verilog Ethernet components for FPGA implementation
nmigen-tutorial - A tutorial for using nmigen
SpinalHDL - Scala based HDL
surf - A huge VHDL library for FPGA development
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
SaxonSoc - SoC based on VexRiscv and ICE40 UP5K
opentitan - OpenTitan: Open source silicon root of trust
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
chisel - Chisel: A Modern Hardware Design Language