sail-riscv
riscv-boom
sail-riscv | riscv-boom | |
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9 | 12 | |
390 | 1,595 | |
2.6% | 1.6% | |
8.2 | 7.2 | |
2 days ago | about 2 months ago | |
Coq | Scala | |
GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
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sail-riscv
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How to improve the RISC-V specification
I've been doing a lot of work with Sail (not SAIL btw) and I'm not sure I agree with the points about it.
There's already a way to extract functions into asciidoc as the author noted. I've used it. It works well.
The liquid types do take some getting used to but they aren't actually used in most of the code; mostly for utility function definitions like `zero_extend`. If you look at the definition for simple instructions they can be very readable and practically pseudocode:
https://github.com/riscv/sail-riscv/blob/0aae5bc7f57df4ebedd...
A lot of instructions are more complex or course but that's what you get if you want to precisely define them.
Overall Sail is a really fantastic language and the liquid types really help avoid bugs.
The biggest actual problems are:
1. The RISC-V spec is chock full of undefined / implementation defined behaviour. How do you capture that in code, where basically everything is defined. The biggest example is probably WARL fields which can do basically anything. Another example is decomposing misaligned accesses. You can decompose them into any number of atomic memory operations and do them in any order. E.g. Spike decomposes them into single byte accesses. (This problem isn't really unique to Sail tbf).
2. The RISC-V Sail model doesn't do a good job of letting you configure it currently. E.g. you can't even set the spec version at the moment. This is just an engineering problem though. We're hoping to fix it one day using riscv-config which is a YAML file that's supposed to specify all the configurable behaviour about a RISC-V chip.
I definitely agree about the often wooly language in the spec though. It doesn't even use RFC-style MUST/SHOULD/MAY terms.
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RISC-V Vector benchmark results
The official formal specification of the Vector Extension has just been merged into the Golden RISC-V model:
https://github.com/riscv/sail-riscv/commit/c90cf2e6eff5fa4ef...
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Cascade: CPU Fuzzing via Intricate Program Generation
the retired instruction counters when written by software.
Funnily enough the Sail model had this bug too! https://github.com/riscv/sail-riscv/issues/256
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Arm’s Cortex A510: Two Kids in a Trench Coat
> loose specification of the RISC-V ISA.
This is being worked on with the Sail model [1]. In order for a RISC-V extension to be ratified it ought to be implemented in Sail. The understanding is also that the RISC-V ISA manual should be built with code snippets from the Sail model (similar to how the Arm Arm is build from ASL definition). The main issue is a lack of people willing and able to write Sail for RISC-V. But that is beginning to change, since RISC-V member companies are increasingly use Sail. As an example, the RISC-V exception type is defined in [2]. Is that precise enough for you?
[1] https://github.com/riscv/sail-riscv
[2] https://github.com/riscv/sail-riscv/blob/master/model/riscv_...
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RISC-V CPU formal specification F# edition
>it allows to formally verify the correctness of a particular ISA
That must be hypothetical. Functionalness of the language doesn't make anything that is written in it automatically subject to formal verification. (mechanized or pen and paper). What kind of correctness properties does it actually allow to formally verify? I understand if it was the F* language, which is a full blown dependently typed proof checker, but with F#, which is defined by the implementation and 300 page English spec, I don't think you can verify anything interesting. As far as I know F# itself doesn't have mechanized formal semantics and its type system could be unsound.
https://github.com/mit-plv/riscv-coq and https://github.com/riscv/sail-riscv (don't know how complete they are) approaches actually allow to formally (mechanically) verify riscv properties.
- 64-bit Arm ∩ 64-bit RISC V
- C++17 RISC-V RV32/64/128 userspace emulator library
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
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Areas to contribute in RISC-V RTL verification
Doing something leveraging the SAIL model would be valuable, as that's the official formal model: https://github.com/rems-project/sail-riscv
riscv-boom
- Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
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Cascade: CPU Fuzzing via Intricate Program Generation
Looks like from Appendix D that only 2 bugs were found in BOOM:
> 1. Inaccurate instruction count when minstret is written by software
I don't know what that means, but having minstret written by software was definitely not something I ever tested. In general, perf counters are likely to be undertested.
> 2. Static rounding is ignored for fdiv.s and fsqrt.s
A mistake was made in only listening to the dynamic rounding mode for the fdiv/sqrt unit. This is one of those bugs that is trivially found if you test for it, but it turns out that no benchmarking ever cared about this and from all of the fuzzers I used when I worked on BOOM, NONE of them hit it (including commercial ones...). Ooops.
Fixed here: https://github.com/riscv-boom/riscv-boom/pull/629/files
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In your opinion, what is the most advanced open source softcore processor?
The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.
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PyXHDL - Python Frontend For VHDL And Verilog
it is used in the Berkley Out-of-Order RISC-V processor: https://github.com/riscv-boom/riscv-boom
- Semidynamics Unveils First Customizable RISC-V Cores for End Users
- TechTechPotato (Dr Ian Cutress): "Building High-Performance RISC-V Cores for Everything"
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Open-source RISC-V CPU projects for contribution
SonicBOOM: https://github.com/riscv-boom/riscv-boom
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The Surprising Subtleties of Zeroing a Register
Some cores are open source and you can see for yourself.
Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala:
https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5...
From RSD, a core designed for FPGAs written in SystemVerilog:
https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R...
And then there's the recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source?
https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
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Fence instruction implementation in BOOM
If you look at the decoder (https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/exu/decode.scala), you can see that the fence instructions are also marked as "unique" instructions. Only one "unique" instruction is allowed in the pipeline at a time.
What are some alternatives?
litmus-tests-riscv - RISC-V architecture concurrency model litmus tests
rocket-chip - Rocket Chip Generator
riscv-isa-sim - Spike, a RISC-V ISA Simulator
openc910 - OpenXuantie - OpenC910 Core
riscv-dv - Random instruction generator for RISC-V processor verification
XiangShan - Open-source high-performance RISC-V processor
riscv-coq - RISC-V Specification in Coq
rsd - RSD: RISC-V Out-of-Order Superscalar Processor
libriscv - C++20 RISC-V RV32/64/128 userspace emulator library
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
force-riscv - Instruction Set Generator initially contributed by Futurewei
Cores-VeeR-EL2 - VeeR EL2 Core