Areas to contribute in RISC-V RTL verification

• sail-riscv

  9 385 7.7 Coq

  Sail RISC-V model

  

Doing something leveraging the SAIL model would be valuable, as that's the official formal model: https://github.com/rems-project/sail-riscv

• litmus-tests-riscv

  1 62 3.6 Assembly

  RISC-V architecture concurrency model litmus tests

  

Or extending work here on the diy / litmus stuff: https://github.com/litmus-tests/litmus-tests-riscv

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

• riscv-config

  1 65 8.4 Python

  RISC-V Configuration Validator

  

Generate architectural coverage models based on https://github.com/riscv/riscv-config

• riscv-dv

  6 949 5.2 Python

  Random instruction generator for RISC-V processor verification

  

• force-riscv

  1 231 3.6 C++

  Instruction Set Generator initially contributed by Futurewei

  

dynamic random instruction generator for riscv

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

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