sail-riscv
libriscv
sail-riscv | libriscv | |
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9 | 16 | |
390 | 411 | |
2.6% | - | |
8.2 | 9.6 | |
2 days ago | 5 days ago | |
Coq | C++ | |
GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
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sail-riscv
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How to improve the RISC-V specification
I've been doing a lot of work with Sail (not SAIL btw) and I'm not sure I agree with the points about it.
There's already a way to extract functions into asciidoc as the author noted. I've used it. It works well.
The liquid types do take some getting used to but they aren't actually used in most of the code; mostly for utility function definitions like `zero_extend`. If you look at the definition for simple instructions they can be very readable and practically pseudocode:
https://github.com/riscv/sail-riscv/blob/0aae5bc7f57df4ebedd...
A lot of instructions are more complex or course but that's what you get if you want to precisely define them.
Overall Sail is a really fantastic language and the liquid types really help avoid bugs.
The biggest actual problems are:
1. The RISC-V spec is chock full of undefined / implementation defined behaviour. How do you capture that in code, where basically everything is defined. The biggest example is probably WARL fields which can do basically anything. Another example is decomposing misaligned accesses. You can decompose them into any number of atomic memory operations and do them in any order. E.g. Spike decomposes them into single byte accesses. (This problem isn't really unique to Sail tbf).
2. The RISC-V Sail model doesn't do a good job of letting you configure it currently. E.g. you can't even set the spec version at the moment. This is just an engineering problem though. We're hoping to fix it one day using riscv-config which is a YAML file that's supposed to specify all the configurable behaviour about a RISC-V chip.
I definitely agree about the often wooly language in the spec though. It doesn't even use RFC-style MUST/SHOULD/MAY terms.
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RISC-V Vector benchmark results
The official formal specification of the Vector Extension has just been merged into the Golden RISC-V model:
https://github.com/riscv/sail-riscv/commit/c90cf2e6eff5fa4ef...
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Cascade: CPU Fuzzing via Intricate Program Generation
the retired instruction counters when written by software.
Funnily enough the Sail model had this bug too! https://github.com/riscv/sail-riscv/issues/256
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Arm’s Cortex A510: Two Kids in a Trench Coat
> loose specification of the RISC-V ISA.
This is being worked on with the Sail model [1]. In order for a RISC-V extension to be ratified it ought to be implemented in Sail. The understanding is also that the RISC-V ISA manual should be built with code snippets from the Sail model (similar to how the Arm Arm is build from ASL definition). The main issue is a lack of people willing and able to write Sail for RISC-V. But that is beginning to change, since RISC-V member companies are increasingly use Sail. As an example, the RISC-V exception type is defined in [2]. Is that precise enough for you?
[1] https://github.com/riscv/sail-riscv
[2] https://github.com/riscv/sail-riscv/blob/master/model/riscv_...
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RISC-V CPU formal specification F# edition
>it allows to formally verify the correctness of a particular ISA
That must be hypothetical. Functionalness of the language doesn't make anything that is written in it automatically subject to formal verification. (mechanized or pen and paper). What kind of correctness properties does it actually allow to formally verify? I understand if it was the F* language, which is a full blown dependently typed proof checker, but with F#, which is defined by the implementation and 300 page English spec, I don't think you can verify anything interesting. As far as I know F# itself doesn't have mechanized formal semantics and its type system could be unsound.
https://github.com/mit-plv/riscv-coq and https://github.com/riscv/sail-riscv (don't know how complete they are) approaches actually allow to formally (mechanically) verify riscv properties.
- 64-bit Arm ∩ 64-bit RISC V
- C++17 RISC-V RV32/64/128 userspace emulator library
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
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Areas to contribute in RISC-V RTL verification
Doing something leveraging the SAIL model would be valuable, as that's the official formal model: https://github.com/rems-project/sail-riscv
libriscv
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Ask HN: Looking for a project to volunteer on? (November 2023)
Seeking: https://github.com/fwsGonzo/libriscv
This is a C++ RISC-V emulator that focuses on isolating a single process, aka userspace emulation. I am currently working mostly on binary translation, and recently I have made a push to move it from experimental state to fully supported. Another experimental feature is embedding libtcc and using that for binary translation. It is fairly fast to compile, and gives decent speedups. The challenge is what to do now that (perhaps) some low hanging fruits have been picked.
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Writing a Tiny RISC-V Emulator [video]
I definitely recommend people to consider the base ISA of RISC-V if they want to try to implement a CPU or even full-system emulation. I understand that implementing a GameBoy emulator might be more attractive because you are working towards something graphical, but you can definitely get something similar with RISC-V, eg. Doom (SDL example: https://github.com/fwsGonzo/libriscv/tree/master/examples/do...)
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MSVC-compatible CMake project
This is the example project: https://github.com/fwsGonzo/libriscv/tree/master/examples/msvc
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MSVC troubles
Pretty much two days of work: https://github.com/fwsGonzo/libriscv/commits/master
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Hacker News top posts: Nov 21, 2022
Show HN: Libriscv – RISC-V userspace emulator library\ (7 comments)
- GitHub - fwsGonzo/libriscv: C++17 RISC-V RV32/64/128 userspace emulator library
- Show HN: C++17 RISC-V RV32/64/128 userspace emulator library
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C++17 RISC-V RV32/64/128 userspace emulator library
There is a doom emulation demo here now: https://github.com/fwsGonzo/libriscv/tree/master/emulator/do...
You will need to add the shareware doom1.wad yourself. :)
What are some alternatives?
litmus-tests-riscv - RISC-V architecture concurrency model litmus tests
chrgfx - Converts to and from tile based graphics from retro video game hardware
riscv-isa-sim - Spike, a RISC-V ISA Simulator
stduuid - A C++17 cross-platform implementation for UUIDs
riscv-dv - Random instruction generator for RISC-V processor verification
lager - C++ library for value-oriented design using the unidirectional data-flow architecture — Redux for C++
riscv-coq - RISC-V Specification in Coq
seer - Seer - a gui frontend to gdb
force-riscv - Instruction Set Generator initially contributed by Futurewei
nomenus-rex - A CLI utility for the file mass-renaming
Forvis_RISCV-ISA-Spec - Formal specification of RISC-V Instruction Set
GPU-Raytracer - GPU Raytracer from scratch in C++/CUDA