riscv-boom
chipyard
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riscv-boom | chipyard | |
---|---|---|
12 | 5 | |
1,593 | 1,428 | |
3.0% | 4.3% | |
7.2 | 9.7 | |
about 1 month ago | 3 days ago | |
Scala | Scala | |
BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-boom
- Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
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Cascade: CPU Fuzzing via Intricate Program Generation
Looks like from Appendix D that only 2 bugs were found in BOOM:
> 1. Inaccurate instruction count when minstret is written by software
I don't know what that means, but having minstret written by software was definitely not something I ever tested. In general, perf counters are likely to be undertested.
> 2. Static rounding is ignored for fdiv.s and fsqrt.s
A mistake was made in only listening to the dynamic rounding mode for the fdiv/sqrt unit. This is one of those bugs that is trivially found if you test for it, but it turns out that no benchmarking ever cared about this and from all of the fuzzers I used when I worked on BOOM, NONE of them hit it (including commercial ones...). Ooops.
Fixed here: https://github.com/riscv-boom/riscv-boom/pull/629/files
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In your opinion, what is the most advanced open source softcore processor?
The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.
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PyXHDL - Python Frontend For VHDL And Verilog
it is used in the Berkley Out-of-Order RISC-V processor: https://github.com/riscv-boom/riscv-boom
- Semidynamics Unveils First Customizable RISC-V Cores for End Users
- TechTechPotato (Dr Ian Cutress): "Building High-Performance RISC-V Cores for Everything"
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Open-source RISC-V CPU projects for contribution
SonicBOOM: https://github.com/riscv-boom/riscv-boom
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The Surprising Subtleties of Zeroing a Register
Some cores are open source and you can see for yourself.
Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala:
https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5...
From RSD, a core designed for FPGAs written in SystemVerilog:
https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R...
And then there's the recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source?
https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
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Fence instruction implementation in BOOM
If you look at the decoder (https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/exu/decode.scala), you can see that the fence instructions are also marked as "unique" instructions. Only one "unique" instruction is allowed in the pipeline at a time.
chipyard
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Chisel: A Modern Hardware Design Language
It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.
Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.
Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.
[0]: https://github.com/ucb-bar/chipyard
[1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...
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A repository that tracks upstream but allows separate tracking.
The repo in question is chipyard: https://github.com/ucb-bar/chipyard
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Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.
If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.
[1] https://github.com/ucb-bar/chipyard
[2] https://github.com/SpinalHDL/SpinalHDL
[3] https://github.com/B-Lang-org/bsc
- Chipyard: An Open Source RISC-V SoC Design Framework
- How to use a RISC V core for other purposes?
What are some alternatives?
rocket-chip - Rocket Chip Generator
openc910 - OpenXuantie - OpenC910 Core
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
XiangShan - Open-source high-performance RISC-V processor
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
rsd - RSD: RISC-V Out-of-Order Superscalar Processor
RVVM - The RISC-V Virtual Machine
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
nuclei-sdk - Nuclei RISC-V Software Development Kit
Cores-VeeR-EL2 - VeeR EL2 Core
shecc - A self-hosting and educational C optimizing compiler