quasiSoC
chipyard
| quasiSoC | chipyard | |
|---|---|---|
| 1 | 5 | |
| 91 | 1,432 | |
| - | 3.1% | |
| 6.4 | 9.7 | |
| 10 days ago | 2 days ago | |
| C | Scala | |
| GNU General Public License v3.0 only | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
quasiSoC
chipyard
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Chisel: A Modern Hardware Design Language
It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.
Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.
Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.
[0]: https://github.com/ucb-bar/chipyard
[1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...
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A repository that tracks upstream but allows separate tracking.
The repo in question is chipyard: https://github.com/ucb-bar/chipyard
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Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system
Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.
If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.
[1] https://github.com/ucb-bar/chipyard
[2] https://github.com/SpinalHDL/SpinalHDL
[3] https://github.com/B-Lang-org/bsc
- Chipyard: An Open Source RISC-V SoC Design Framework
- How to use a RISC V core for other purposes?
What are some alternatives?
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
rocket-chip - Rocket Chip Generator
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
RVVM - The RISC-V Virtual Machine
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
rt-thread - RT-Thread is an open source IoT real-time operating system (RTOS).
nuclei-sdk - Nuclei RISC-V Software Development Kit
shecc - A self-hosting and educational C optimizing compiler